target/mips: Implement CP0.Config7.WII bit support
Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230216051717.3911212-4-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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@ -333,6 +333,7 @@ const mips_def_t mips_defs[] =
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.CP0_Config1 = MIPS_CONFIG1,
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
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.CP0_Config7 = 1 << CP0C7_WII,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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@ -354,6 +355,7 @@ const mips_def_t mips_defs[] =
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
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.CP0_Config7 = 1 << CP0C7_WII,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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@ -392,6 +394,7 @@ const mips_def_t mips_defs[] =
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.CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
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(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
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(1 << CP0C5_FRE) | (1 << CP0C5_UFR),
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.CP0_Config7 = 1 << CP0C7_WII,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 0,
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.SYNCI_Step = 32,
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@ -143,11 +143,13 @@ static bool mips_cpu_has_work(CPUState *cs)
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/*
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* Prior to MIPS Release 6 it is implementation dependent if non-enabled
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* interrupts wake-up the CPU, however most of the implementations only
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* check for interrupts that can be taken.
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* check for interrupts that can be taken. For pre-release 6 CPUs,
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* check for CP0 Config7 'Wait IE ignore' bit.
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*/
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_mips_hw_interrupts_pending(env)) {
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if (cpu_mips_hw_interrupts_enabled(env) ||
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(env->CP0_Config7 & (1 << CP0C7_WII)) ||
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(env->insn_flags & ISA_MIPS_R6)) {
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has_work = true;
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}
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@ -980,6 +980,7 @@ typedef struct CPUArchState {
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#define CP0C6_DATAPREF 0
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int32_t CP0_Config7;
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int64_t CP0_Config7_rw_bitmask;
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#define CP0C7_WII 31
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#define CP0C7_NAPCGEN 2
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#define CP0C7_UNIMUEN 1
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#define CP0C7_VFPUCGEN 0
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