target/arm: Add SVE decode skeleton

Including only 4, as-yet unimplemented, instruction patterns
so that the whole thing compiles.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-18 17:48:08 +01:00 committed by Peter Maydell
parent 8c71baedb8
commit 38388f7ee3
5 changed files with 125 additions and 1 deletions

1
.gitignore vendored
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@ -206,3 +206,4 @@ trace-dtrace-root.h
trace-dtrace-root.dtrace trace-dtrace-root.dtrace
trace-ust-all.h trace-ust-all.h
trace-ust-all.c trace-ust-all.c
/target/arm/decode-sve.inc.c

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@ -10,3 +10,13 @@ obj-y += gdbstub.o
obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
obj-y += crypto_helper.o obj-y += crypto_helper.o
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
$(call quiet-command,\
$(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
"GEN", $(TARGET_DIR)$@)
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
obj-$(TARGET_AARCH64) += translate-sve.o

45
target/arm/sve.decode Normal file
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@ -0,0 +1,45 @@
# AArch64 SVE instruction descriptions
#
# Copyright (c) 2017 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
###########################################################################
# Named attribute sets. These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.
&rrr_esz rd rn rm esz
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
# Three operand with unused vector element size
@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
###########################################################################
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated)
AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0

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@ -13676,9 +13676,14 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
s->fp_access_checked = false; s->fp_access_checked = false;
switch (extract32(insn, 25, 4)) { switch (extract32(insn, 25, 4)) {
case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */ case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
unallocated_encoding(s); unallocated_encoding(s);
break; break;
case 0x2:
if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) {
unallocated_encoding(s);
}
break;
case 0x8: case 0x9: /* Data processing - immediate */ case 0x8: case 0x9: /* Data processing - immediate */
disas_data_proc_imm(s, insn); disas_data_proc_imm(s, insn);
break; break;

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@ -0,0 +1,63 @@
/*
* AArch64 SVE translation
*
* Copyright (c) 2018 Linaro, Ltd
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "arm_ldst.h"
#include "translate.h"
#include "internals.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/log.h"
#include "trace-tcg.h"
#include "translate-a64.h"
/*
* Include the generated decoder.
*/
#include "decode-sve.inc.c"
/*
* Implement all of the translator functions referenced by the decoder.
*/
static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn)
{
return false;
}
static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn)
{
return false;
}
static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn)
{
return false;
}
static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn)
{
return false;
}