Fix ARM host TLB.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook
parent
e6bb7d7efd
commit
3979144c49
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@ -90,8 +90,6 @@ static inline int tcg_target_get_call_iarg_regs_count(int flags)
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return 4;
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}
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#define USE_TLB
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/* parse target specific constraints */
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int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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@ -115,22 +113,8 @@ int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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case 'x':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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# ifdef USE_TLB
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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# endif
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break;
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/* qemu_ld/st data_reg */
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case 'd':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r0 and optionally r1 will be overwritten by the address
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* so don't use these. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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# if TARGET_LONG_BITS == 64 || defined(USE_TLB)
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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# endif
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break;
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/* qemu_ld/st64 data_reg2 */
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@ -153,9 +137,7 @@ int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r0 will be overwritten by the low word of base, so don't use it. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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# ifdef USE_TLB
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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# endif
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break;
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# endif
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#endif
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@ -210,6 +192,7 @@ enum arm_data_opc_e {
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ARITH_ADC = 0x5,
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ARITH_SBC = 0x6,
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ARITH_RSC = 0x7,
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ARITH_TST = 0x8,
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ARITH_CMP = 0xa,
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ARITH_CMN = 0xb,
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ARITH_ORR = 0xc,
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@ -218,7 +201,8 @@ enum arm_data_opc_e {
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ARITH_MVN = 0xf,
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};
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#define TO_CPSR(opc) ((opc == ARITH_CMP || opc == ARITH_CMN) << 20)
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#define TO_CPSR(opc) \
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((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
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#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
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#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
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@ -309,7 +293,7 @@ static inline void tcg_out_dat_reg2(TCGContext *s,
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static inline void tcg_out_dat_imm(TCGContext *s,
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int cond, int opc, int rd, int rn, int im)
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{
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tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) |
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tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
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(rn << 16) | (rd << 12) | im);
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}
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@ -428,6 +412,21 @@ static inline void tcg_out_st32_r(TCGContext *s, int cond,
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(rn << 16) | (rd << 12) | rm);
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}
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/* Register pre-increment with base writeback. */
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static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
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int rd, int rn, int rm)
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{
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tcg_out32(s, (cond << 28) | 0x07b00000 |
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(rn << 16) | (rd << 12) | rm);
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}
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static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
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int rd, int rn, int rm)
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{
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tcg_out32(s, (cond << 28) | 0x07a00000 |
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(rn << 16) | (rd << 12) | rm);
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}
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static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
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int rd, int rn, tcg_target_long im)
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{
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@ -826,6 +825,8 @@ static void *qemu_st_helpers[4] = {
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};
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#endif
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#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
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static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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const TCGArg *args, int opc)
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{
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@ -835,9 +836,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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# if TARGET_LONG_BITS == 64
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int addr_reg2;
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# endif
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# ifdef USE_TLB
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uint32_t *label_ptr;
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# endif
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#endif
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data_reg = *args++;
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@ -853,17 +852,16 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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mem_index = *args;
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s_bits = opc & 3;
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# ifdef USE_TLB
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/* Should generate something like the following:
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* ror r8, addr_reg, #TARGET_PAGE_BITS
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* shr r8, addr_reg, #TARGET_PAGE_BITS
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* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
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* add r0, T0, r0 lsl #CPU_TLB_ENTRY_BITS
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* add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
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*/
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# if CPU_TLB_BITS > 8
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# error
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# endif
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
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8, 0, addr_reg, SHIFT_IMM_ROR(TARGET_PAGE_BITS));
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8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_imm(s, COND_AL, ARITH_AND,
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0, 8, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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@ -875,7 +873,6 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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* add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
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* before.
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*/
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# define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
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if (mem_index)
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
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(mem_index << (TLB_SHIFT & 1)) |
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@ -884,11 +881,10 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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offsetof(CPUState, tlb_table[0][0].addr_read));
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
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0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* TODO: alignment check?
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* if (s_bits)
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* tcg_out_data_reg(s, COND_EQ, ARITH_EOR,
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* 0, 1, 8, SHIFT_IMM_LSR(32 - s_bits));
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*/
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/* Check alignment. */
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if (s_bits)
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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0, addr_reg, (1 << s_bits) - 1);
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# if TARGET_LONG_BITS == 64
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/* XXX: possibly we could use a block data load or writeback in
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* the first access. */
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@ -918,15 +914,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
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break;
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case 3:
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/* TODO: must write back */
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tcg_out_ld32_r(s, COND_EQ, data_reg, 1, addr_reg);
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tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
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tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
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break;
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}
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label_ptr = (void *) s->code_ptr;
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tcg_out_b(s, COND_EQ, 8);
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# endif
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# ifdef SAVE_LR
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tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
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@ -969,12 +963,11 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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data_reg, 0, 0, SHIFT_IMM_LSL(0));
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break;
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case 3:
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tcg_out_dat_reg(s, cond, ARITH_MOV,
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data_reg, 0, 0, SHIFT_IMM_LSL(0));
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if (data_reg2 != 1)
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tcg_out_dat_reg(s, cond, ARITH_MOV,
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data_reg2, 0, 1, SHIFT_IMM_LSL(0));
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if (data_reg != 0)
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tcg_out_dat_reg(s, cond, ARITH_MOV,
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data_reg, 0, 0, SHIFT_IMM_LSL(0));
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break;
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}
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@ -982,9 +975,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
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tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
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# endif
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# ifdef USE_TLB
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*label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
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# endif
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#else
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switch (opc) {
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case 0:
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@ -1021,9 +1012,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
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# if TARGET_LONG_BITS == 64
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int addr_reg2;
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# endif
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# ifdef USE_TLB
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uint32_t *label_ptr;
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# endif
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#endif
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data_reg = *args++;
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@ -1039,14 +1028,13 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
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mem_index = *args;
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s_bits = opc & 3;
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# ifdef USE_TLB
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/* Should generate something like the following:
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* ror r8, addr_reg, #TARGET_PAGE_BITS
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* shr r8, addr_reg, #TARGET_PAGE_BITS
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* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
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* add r0, T0, r0 lsl #CPU_TLB_ENTRY_BITS
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* add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
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*/
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
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8, 0, addr_reg, SHIFT_IMM_ROR(TARGET_PAGE_BITS));
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8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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tcg_out_dat_imm(s, COND_AL, ARITH_AND,
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0, 8, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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@ -1066,11 +1054,10 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
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offsetof(CPUState, tlb_table[0][0].addr_write));
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
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0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* TODO: alignment check?
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* if (s_bits)
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* tcg_out_data_reg(s, COND_EQ, ARITH_EOR,
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* 0, 1, 8, SHIFT_IMM_LSR(32 - s_bits));
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*/
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/* Check alignment. */
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if (s_bits)
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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0, addr_reg, (1 << s_bits) - 1);
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# if TARGET_LONG_BITS == 64
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/* XXX: possibly we could use a block data load or writeback in
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* the first access. */
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@ -1101,15 +1088,13 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
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tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
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break;
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case 3:
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/* TODO: must write back */
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tcg_out_st32_r(s, COND_EQ, data_reg, 1, addr_reg);
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tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
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tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
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break;
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}
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label_ptr = (void *) s->code_ptr;
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tcg_out_b(s, COND_EQ, 8);
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# endif
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/* TODO: move this code to where the constants pool will be */
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if (addr_reg)
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@ -1195,9 +1180,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond,
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tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
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# endif
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# ifdef USE_TLB
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*label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
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# endif
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#else
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switch (opc) {
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case 0:
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@ -1512,12 +1495,12 @@ static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_qemu_ld16u, { "r", "x", "X" } },
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{ INDEX_op_qemu_ld16s, { "r", "x", "X" } },
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{ INDEX_op_qemu_ld32u, { "r", "x", "X" } },
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{ INDEX_op_qemu_ld64, { "r", "d", "x", "X" } },
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{ INDEX_op_qemu_ld64, { "x", "r", "x", "X" } },
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{ INDEX_op_qemu_st8, { "d", "x", "X" } },
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{ INDEX_op_qemu_st16, { "d", "x", "X" } },
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{ INDEX_op_qemu_st32, { "d", "x", "X" } },
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{ INDEX_op_qemu_st64, { "d", "D", "x", "X" } },
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{ INDEX_op_qemu_st8, { "x", "x", "X" } },
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{ INDEX_op_qemu_st16, { "x", "x", "X" } },
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{ INDEX_op_qemu_st32, { "x", "x", "X" } },
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{ INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
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{ INDEX_op_ext8s_i32, { "r", "r" } },
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{ INDEX_op_ext16s_i32, { "r", "r" } },
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