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target/mips: Use GPR move functions in gen_HILO1_tx79()

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We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-8-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-14 18:58:37 +01:00
parent 61f4e0ec0d
commit 3bc313c4f5
1 changed files with 4 additions and 17 deletions
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21
target/mips/translate.c
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@ -4126,31 +4126,18 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
/* Copy GPR to and from TX79 HI1/LO1 register. */ /* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{ {
if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) {
/* Treat as NOP. */
return;
}
switch (opc) { switch (opc) {
case MMI_OPC_MFHI1: case MMI_OPC_MFHI1:
tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); gen_store_gpr(cpu_HI[1], reg);
break; break;
case MMI_OPC_MFLO1: case MMI_OPC_MFLO1:
tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); gen_store_gpr(cpu_LO[1], reg);
break; break;
case MMI_OPC_MTHI1: case MMI_OPC_MTHI1:
if (reg != 0) { gen_load_gpr(cpu_HI[1], reg);
tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
} else {
tcg_gen_movi_tl(cpu_HI[1], 0);
}
break; break;
case MMI_OPC_MTLO1: case MMI_OPC_MTLO1:
if (reg != 0) { gen_load_gpr(cpu_LO[1], reg);
tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
} else {
tcg_gen_movi_tl(cpu_LO[1], 0);
}
break; break;
default: default:
MIPS_INVAL("mfthilo1 TX79"); MIPS_INVAL("mfthilo1 TX79");