Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3146 c046a42c-6fe2-441c-8c8c-71466251a162
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c92843b5df
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@ -369,7 +369,8 @@ void do_interrupt (CPUState *env)
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}
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}
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enter_debug_mode:
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM;
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env->hflags |= MIPS_HFLAG_DM;
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env->hflags |= MIPS_HFLAG_64;
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if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
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env->hflags |= MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_UM;
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env->hflags &= ~MIPS_HFLAG_UM;
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/* EJTAG probe trap enable is not implemented... */
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/* EJTAG probe trap enable is not implemented... */
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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@ -395,7 +396,8 @@ void do_interrupt (CPUState *env)
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env->CP0_ErrorEPC = env->PC;
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env->CP0_ErrorEPC = env->PC;
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}
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}
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->hflags |= MIPS_HFLAG_64;
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if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
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env->hflags |= MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_UM;
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env->hflags &= ~MIPS_HFLAG_UM;
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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@ -494,7 +496,8 @@ void do_interrupt (CPUState *env)
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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}
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env->CP0_Status |= (1 << CP0St_EXL);
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env->CP0_Status |= (1 << CP0St_EXL);
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env->hflags |= MIPS_HFLAG_64;
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if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
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env->hflags |= MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_UM;
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env->hflags &= ~MIPS_HFLAG_UM;
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}
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}
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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@ -1358,9 +1358,10 @@ void op_mtc0_status (void)
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(val & (1 << CP0St_UM)))
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(val & (1 << CP0St_UM)))
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env->hflags |= MIPS_HFLAG_UM;
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env->hflags |= MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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if ((env->hflags & MIPS_HFLAG_UM) &&
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if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
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((env->hflags & MIPS_HFLAG_UM) &&
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!(val & (1 << CP0St_PX)) &&
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!(val & (1 << CP0St_PX)) &&
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!(val & (1 << CP0St_UX)))
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!(val & (1 << CP0St_UX))))
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env->hflags &= ~MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_64;
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#endif
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#endif
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if (val & (1 << CP0St_CU1))
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if (val & (1 << CP0St_CU1))
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@ -2318,9 +2319,10 @@ void op_eret (void)
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(env->CP0_Status & (1 << CP0St_UM)))
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(env->CP0_Status & (1 << CP0St_UM)))
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env->hflags |= MIPS_HFLAG_UM;
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env->hflags |= MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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if ((env->hflags & MIPS_HFLAG_UM) &&
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if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
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((env->hflags & MIPS_HFLAG_UM) &&
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!(env->CP0_Status & (1 << CP0St_PX)) &&
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!(env->CP0_Status & (1 << CP0St_PX)) &&
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!(env->CP0_Status & (1 << CP0St_UX)))
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!(env->CP0_Status & (1 << CP0St_UX))))
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env->hflags &= ~MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_64;
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#endif
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#endif
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if (loglevel & CPU_LOG_EXEC)
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if (loglevel & CPU_LOG_EXEC)
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@ -2341,9 +2343,10 @@ void op_deret (void)
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(env->CP0_Status & (1 << CP0St_UM)))
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(env->CP0_Status & (1 << CP0St_UM)))
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env->hflags |= MIPS_HFLAG_UM;
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env->hflags |= MIPS_HFLAG_UM;
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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if ((env->hflags & MIPS_HFLAG_UM) &&
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if (!(env->CP0_Config0 & (0x3 << CP0C0_AT)) ||
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((env->hflags & MIPS_HFLAG_UM) &&
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!(env->CP0_Status & (1 << CP0St_PX)) &&
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!(env->CP0_Status & (1 << CP0St_PX)) &&
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!(env->CP0_Status & (1 << CP0St_UX)))
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!(env->CP0_Status & (1 << CP0St_UX))))
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env->hflags &= ~MIPS_HFLAG_64;
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env->hflags &= ~MIPS_HFLAG_64;
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#endif
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#endif
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if (loglevel & CPU_LOG_EXEC)
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if (loglevel & CPU_LOG_EXEC)
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@ -2225,6 +2225,8 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
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switch (sel) {
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switch (sel) {
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case 0:
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case 0:
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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if (!(ctx->hflags & MIPS_HFLAG_64))
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goto die;
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gen_op_mfc0_xcontext();
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gen_op_mfc0_xcontext();
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rn = "XContext";
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rn = "XContext";
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break;
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break;
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@ -2781,6 +2783,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
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switch (sel) {
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switch (sel) {
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case 0:
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case 0:
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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if (!(ctx->hflags & MIPS_HFLAG_64))
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goto die;
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gen_op_mtc0_xcontext();
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gen_op_mtc0_xcontext();
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rn = "XContext";
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rn = "XContext";
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break;
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break;
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@ -3331,11 +3335,9 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
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case 20:
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case 20:
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switch (sel) {
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switch (sel) {
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case 0:
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case 0:
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#ifdef TARGET_MIPS64
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gen_op_dmfc0_xcontext();
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gen_op_dmfc0_xcontext();
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rn = "XContext";
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rn = "XContext";
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break;
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break;
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#endif
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default:
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default:
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goto die;
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goto die;
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}
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}
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@ -3878,11 +3880,9 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
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case 20:
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case 20:
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switch (sel) {
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switch (sel) {
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case 0:
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case 0:
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#ifdef TARGET_MIPS64
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gen_op_mtc0_xcontext();
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gen_op_mtc0_xcontext();
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rn = "XContext";
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rn = "XContext";
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break;
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break;
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#endif
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default:
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default:
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goto die;
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goto die;
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}
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}
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@ -4107,6 +4107,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
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break;
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break;
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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case OPC_DMFC0:
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case OPC_DMFC0:
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if (!(ctx->hflags & MIPS_HFLAG_64))
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generate_exception(ctx, EXCP_RI);
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if (rt == 0) {
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if (rt == 0) {
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/* Treat as NOP */
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/* Treat as NOP */
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return;
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return;
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@ -4116,6 +4118,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
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opn = "dmfc0";
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opn = "dmfc0";
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break;
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break;
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case OPC_DMTC0:
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case OPC_DMTC0:
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if (!(ctx->hflags & MIPS_HFLAG_64))
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generate_exception(ctx, EXCP_RI);
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GEN_LOAD_REG_TN(T0, rt);
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GEN_LOAD_REG_TN(T0, rt);
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gen_dmtc0(env,ctx, rd, ctx->opcode & 0x7);
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gen_dmtc0(env,ctx, rd, ctx->opcode & 0x7);
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opn = "dmtc0";
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opn = "dmtc0";
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@ -6183,11 +6187,7 @@ void cpu_reset (CPUMIPSState *env)
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} else {
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} else {
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env->CP0_ErrorEPC = env->PC;
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env->CP0_ErrorEPC = env->PC;
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}
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}
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#ifdef TARGET_MIPS64
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env->hflags = MIPS_HFLAG_64;
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#else
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env->hflags = 0;
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env->hflags = 0;
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#endif
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env->PC = (int32_t)0xBFC00000;
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env->PC = (int32_t)0xBFC00000;
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env->CP0_Wired = 0;
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env->CP0_Wired = 0;
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/* SMP not implemented */
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/* SMP not implemented */
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@ -86,7 +86,6 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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.Status_rw_bitmask = 0x3278FF17,
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.SEGBITS = 32,
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},
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},
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{
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{
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.name = "4KEcR1",
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.name = "4KEcR1",
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@ -100,7 +99,6 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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.Status_rw_bitmask = 0x3278FF17,
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.SEGBITS = 32,
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},
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},
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{
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{
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.name = "4KEc",
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.name = "4KEc",
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@ -114,7 +112,6 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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.Status_rw_bitmask = 0x3278FF17,
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.SEGBITS = 32,
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},
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},
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{
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{
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.name = "24Kc",
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.name = "24Kc",
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@ -128,7 +125,6 @@ static mips_def_t mips_defs[] =
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.SYNCI_Step = 32,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CCRes = 2,
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.Status_rw_bitmask = 0x3278FF17,
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.Status_rw_bitmask = 0x3278FF17,
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.SEGBITS = 32,
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},
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},
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{
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{
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.name = "24Kf",
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.name = "24Kf",
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@ -144,7 +140,6 @@ static mips_def_t mips_defs[] =
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.Status_rw_bitmask = 0x3678FF17,
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.Status_rw_bitmask = 0x3678FF17,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.SEGBITS = 32,
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},
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},
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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{
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{
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@ -293,8 +288,15 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
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env->Status_rw_bitmask = def->Status_rw_bitmask;
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env->Status_rw_bitmask = def->Status_rw_bitmask;
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env->fcr0 = def->CP1_fcr0;
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env->fcr0 = def->CP1_fcr0;
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#ifdef TARGET_MIPS64
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#ifdef TARGET_MIPS64
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env->SEGBITS = def->SEGBITS;
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if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
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env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
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{
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env->hflags |= MIPS_HFLAG_64;
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env->SEGBITS = def->SEGBITS;
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env->SEGMask = (3ULL << 62) | ((1ULL << def->SEGBITS) - 1);
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} else {
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env->SEGBITS = 32;
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env->SEGMask = 0xFFFFFFFF;
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}
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#endif
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#endif
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#ifdef CONFIG_USER_ONLY
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#ifdef CONFIG_USER_ONLY
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if (env->CP0_Config1 & (1 << CP0C1_FP))
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if (env->CP0_Config1 & (1 << CP0C1_FP))
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