OpenE2K/qemu-e2k
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misc: Use new rotate functions

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Signed-off-by: Stefan Weil <sw@weilnetz.de>
This commit is contained in:
Stefan Weil 2013-09-12 21:13:13 +02:00
parent 6aa25b4a7b
commit 3df2b8fde9
3 changed files with 9 additions and 13 deletions
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2
target-arm/iwmmxt_helper.c
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@ -577,7 +577,7 @@ uint64_t HELPER(iwmmxt_rorl)(CPUARMState *env, uint64_t x, uint32_t n)
uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n) uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n)
{ {
x = (x >> n) | (x << (64 - n)); x = ror64(x, n);
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x); env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
return x; return x;
} }

12
tcg/optimize.c
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@ -238,20 +238,16 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
return (int64_t)x >> (int64_t)y; return (int64_t)x >> (int64_t)y;
case INDEX_op_rotr_i32: case INDEX_op_rotr_i32:
x = ((uint32_t)x << (32 - y)) | ((uint32_t)x >> y); return ror32(x, y);
return x;
case INDEX_op_rotr_i64: case INDEX_op_rotr_i64:
x = ((uint64_t)x << (64 - y)) | ((uint64_t)x >> y); return ror64(x, y);
return x;
case INDEX_op_rotl_i32: case INDEX_op_rotl_i32:
x = ((uint32_t)x << y) | ((uint32_t)x >> (32 - y)); return rol32(x, y);
return x;
case INDEX_op_rotl_i64: case INDEX_op_rotl_i64:
x = ((uint64_t)x << y) | ((uint64_t)x >> (64 - y)); return rol64(x, y);
return x;
CASE_OP_32_64(not): CASE_OP_32_64(not):
return ~x; return ~x;

8
tci.c
View File

@ -688,13 +688,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr); t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2))); tci_write_reg32(t0, rol32(t1, t2));
break; break;
case INDEX_op_rotr_i32: case INDEX_op_rotr_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_ri32(&tb_ptr); t1 = tci_read_ri32(&tb_ptr);
t2 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr);
tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2))); tci_write_reg32(t0, ror32(t1, t2));
break; break;
#endif #endif
#if TCG_TARGET_HAS_deposit_i32 #if TCG_TARGET_HAS_deposit_i32
@ -955,13 +955,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr); t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr); t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, (t1 << t2) | (t1 >> (64 - t2))); tci_write_reg64(t0, rol64(t1, t2));
break; break;
case INDEX_op_rotr_i64: case INDEX_op_rotr_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_ri64(&tb_ptr); t1 = tci_read_ri64(&tb_ptr);
t2 = tci_read_ri64(&tb_ptr); t2 = tci_read_ri64(&tb_ptr);
tci_write_reg64(t0, (t1 >> t2) | (t1 << (64 - t2))); tci_write_reg64(t0, ror64(t1, t2));
break; break;
#endif #endif
#if TCG_TARGET_HAS_deposit_i64 #if TCG_TARGET_HAS_deposit_i64