target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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riscv_set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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riscv_set_feature(env, RISCV_FEATURE_PMP);
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}
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if (cpu->cfg.epmp && !cpu->cfg.pmp) {
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/*
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* Enhanced PMP should only be available
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@ -87,7 +87,6 @@
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so a cpu features bitfield is required, likewise for optional PMP support */
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enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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};
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/* Privileged specification version */
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@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
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pmp_priv_t pmp_priv;
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int pmp_index = -1;
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if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
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if (!riscv_cpu_cfg(env)->pmp) {
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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}
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@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
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static RISCVException pmp(CPURISCVState *env, int csrno)
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{
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if (riscv_feature(env, RISCV_FEATURE_PMP)) {
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if (riscv_cpu_cfg(env)->pmp) {
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return RISCV_EXCP_NONE;
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}
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@ -27,9 +27,8 @@
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static bool pmp_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_feature(env, RISCV_FEATURE_PMP);
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return cpu->cfg.pmp;
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}
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static int pmp_post_load(void *opaque, int version_id)
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@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env)
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uint64_t mstatus = env->mstatus;
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target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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if (riscv_cpu_cfg(env)->pmp &&
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!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
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}
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@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
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}
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}
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if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
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if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
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/*
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* Privileged spec v1.10 states if HW doesn't implement any PMP entry
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* or no PMP entry matches an M-Mode access, the access succeeds.
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