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target/riscv: remove RISCV_FEATURE_EPMP 

RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
flag. Use the flag directly.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-02-22 15:52:01 -03:00 committed by Palmer Dabbelt
parent 09631441e5
commit 6a3ffda2ba
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
4 changed files with 6 additions and 11 deletions
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10
target/riscv/cpu.c
View File

@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_set_feature(env, RISCV_FEATURE_PMP);
}
if (cpu->cfg.epmp) {
riscv_set_feature(env, RISCV_FEATURE_EPMP);
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
if (!cpu->cfg.pmp) {
error_setg(errp, "Invalid configuration: EPMP requires PMP support");
return;
}
error_setg(errp, "Invalid configuration: EPMP requires PMP support");
return;
}

1
target/riscv/cpu.h
View File

@ -88,7 +88,6 @@
enum {
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
};
/* Privileged specification version */

2
target/riscv/csr.c
View File

@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
static RISCVException epmp(CPURISCVState *env, int csrno)
{
if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
return RISCV_EXCP_NONE;
}

4
target/riscv/pmp.c
View File

@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
if (riscv_cpu_cfg(env)->epmp) {
/* mseccfg.RLB is set */
if (MSECCFG_RLB_ISSET(env)) {
locked = false;
@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
{
bool ret;
if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
if (riscv_cpu_cfg(env)->epmp) {
if (MSECCFG_MMWP_ISSET(env)) {
/*
* The Machine Mode Whitelist Policy (mseccfg.MMWP) is set