target/riscv: remove RISCV_FEATURE_EPMP
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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riscv_set_feature(env, RISCV_FEATURE_PMP);
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}
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if (cpu->cfg.epmp) {
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riscv_set_feature(env, RISCV_FEATURE_EPMP);
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if (cpu->cfg.epmp && !cpu->cfg.pmp) {
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/*
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* Enhanced PMP should only be available
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* on harts with PMP support
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*/
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if (!cpu->cfg.pmp) {
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error_setg(errp, "Invalid configuration: EPMP requires PMP support");
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return;
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}
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error_setg(errp, "Invalid configuration: EPMP requires PMP support");
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return;
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}
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@ -88,7 +88,6 @@
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enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_EPMP,
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};
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/* Privileged specification version */
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@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
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static RISCVException epmp(CPURISCVState *env, int csrno)
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{
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if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
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if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
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return RISCV_EXCP_NONE;
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}
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@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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if (pmp_index < MAX_RISCV_PMPS) {
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bool locked = true;
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if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
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if (riscv_cpu_cfg(env)->epmp) {
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/* mseccfg.RLB is set */
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if (MSECCFG_RLB_ISSET(env)) {
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locked = false;
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@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
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{
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bool ret;
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if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
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if (riscv_cpu_cfg(env)->epmp) {
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if (MSECCFG_MMWP_ISSET(env)) {
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/*
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* The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
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