hw/riscv: hart: Add a new 'resetvec' property
RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -31,6 +31,8 @@ static Property riscv_harts_props[] = {
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
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DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
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DEFAULT_RSTVEC),
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DEFINE_PROP_END_OF_LIST(),
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DEFINE_PROP_END_OF_LIST(),
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};
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};
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@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
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char *cpu_type, Error **errp)
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char *cpu_type, Error **errp)
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{
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{
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
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object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
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qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
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s->harts[idx].env.mhartid = s->hartid_base + idx;
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s->harts[idx].env.mhartid = s->hartid_base + idx;
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
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return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
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return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
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@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState {
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uint32_t num_harts;
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uint32_t num_harts;
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uint32_t hartid_base;
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uint32_t hartid_base;
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char *cpu_type;
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char *cpu_type;
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uint64_t resetvec;
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RISCVCPU *harts;
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RISCVCPU *harts;
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} RISCVHartArrayState;
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} RISCVHartArrayState;
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