RISC-V: Adding XTheadBb ISA extension
This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
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ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
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ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
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ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
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ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
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ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
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ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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@ -1092,6 +1093,7 @@ static Property riscv_cpu_extensions[] = {
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/* Vendor-specific custom extensions */
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DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
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DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
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DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
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DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
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DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
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@ -474,6 +474,7 @@ struct RISCVCPUConfig {
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/* Vendor-specific custom extensions */
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bool ext_xtheadba;
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bool ext_xtheadbb;
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bool ext_xtheadcmo;
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bool ext_xtheadsync;
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bool ext_XVentanaCondOps;
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@ -22,6 +22,12 @@
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} \
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} while (0)
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#define REQUIRE_XTHEADBB(ctx) do { \
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if (!ctx->cfg_ptr->ext_xtheadbb) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_XTHEADCMO(ctx) do { \
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if (!ctx->cfg_ptr->ext_xtheadcmo) { \
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return false; \
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@ -67,6 +73,124 @@ GEN_TRANS_TH_ADDSL(1)
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GEN_TRANS_TH_ADDSL(2)
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GEN_TRANS_TH_ADDSL(3)
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/* XTheadBb */
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/* th.srri is an alternate encoding for rori (from Zbb) */
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static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
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tcg_gen_rotri_tl, gen_roriw, NULL);
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}
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/* th.srriw is an alternate encoding for roriw (from Zbb) */
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static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a)
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{
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REQUIRE_XTHEADBB(ctx);
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REQUIRE_64BIT(ctx);
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ctx->ol = MXL_RV32;
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
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}
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/* th.ext and th.extu perform signed/unsigned bitfield extraction */
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static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a,
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void (*f)(TCGv, TCGv, unsigned int, unsigned int))
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{
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO);
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if (a->lsb <= a->msb) {
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f(dest, source, a->lsb, a->msb - a->lsb + 1);
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gen_set_gpr(ctx, a->rd, dest);
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}
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return true;
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}
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static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl);
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}
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static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_th_bfextract(ctx, a, tcg_gen_extract_tl);
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}
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/* th.ff0: find first zero (clz on an inverted input) */
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static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext)
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{
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv src1 = get_gpr(ctx, a->rs1, ext);
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int olen = get_olen(ctx);
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TCGv t = tcg_temp_new();
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tcg_gen_not_tl(t, src1);
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if (olen != TARGET_LONG_BITS) {
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if (olen == 32) {
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gen_clzw(dest, t);
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} else {
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g_assert_not_reached();
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}
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} else {
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gen_clz(dest, t);
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}
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tcg_temp_free(t);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_th_ff0(ctx, a, EXT_NONE);
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}
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/* th.ff1 is an alternate encoding for clz (from Zbb) */
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static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
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}
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static void gen_th_revw(TCGv ret, TCGv arg1)
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{
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tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS);
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}
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/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */
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static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_revw);
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}
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/* th.revw is a sign-extended byte-swap of the lower word */
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static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a)
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{
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REQUIRE_XTHEADBB(ctx);
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REQUIRE_64BIT(ctx);
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return gen_unary(ctx, a, EXT_NONE, gen_th_revw);
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}
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/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */
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static void gen_th_tstnbz(TCGv ret, TCGv source1)
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{
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gen_orc_b(ret, source1);
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tcg_gen_not_tl(ret, ret);
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}
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static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a)
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{
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REQUIRE_XTHEADBB(ctx);
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return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz);
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}
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/* XTheadCmo */
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static inline int priv_level(DisasContext *ctx)
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@ -132,8 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
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static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
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{
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return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
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ctx->cfg_ptr->ext_xtheadsync;
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return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
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ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
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}
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#define MATERIALISE_EXT_PREDICATE(ext) \
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@ -13,14 +13,23 @@
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%rd 7:5
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%rs1 15:5
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%rs2 20:5
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%sh5 20:5
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%sh6 20:6
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# Argument sets
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&r rd rs1 rs2 !extern
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&r2 rd rs1 !extern
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&shift shamt rs1 rd !extern
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&th_bfext msb lsb rs1 rd
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# Formats
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
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@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
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@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd
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@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
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@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
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# XTheadBa
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# Instead of defining a new encoding, we simply use the decoder to
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@ -38,6 +47,17 @@ th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r
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th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r
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th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r
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# XTheadBb
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th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext
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th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext
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th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2
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th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2
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th_srri 000100 ...... ..... 001 ..... 0001011 @sh6
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th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5
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th_rev 1000001 00000 ..... 001 ..... 0001011 @r2
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th_revw 1001000 00000 ..... 001 ..... 0001011 @r2
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th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2
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# XTheadCmo
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th_dcache_call 0000000 00001 00000 000 00000 0001011
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th_dcache_ciall 0000000 00011 00000 000 00000 0001011
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