OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

riscv: spelling fixes

Browse Source 
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Michael Tokarev 2023-07-14 14:19:10 +03:00
parent 6c67d98c4a
commit 42fe74998c
11 changed files with 21 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/riscv/microchip_pfsoc.c
View File

@ -659,7 +659,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
mc->default_ram_id = "microchip.icicle.kit.ram";
/*
* Map 513 MiB high memory, the mimimum required high memory size, because
* Map 513 MiB high memory, the minimum required high memory size, because
* HSS will do memory test against the high memory address range regardless
* of physical memory installed.
*

4
hw/riscv/virt.c
View File

@ -66,13 +66,13 @@
#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
#if VIRT_IMSIC_GROUP_MAX_SIZE < \
IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
#error "Can't accomodate single IMSIC group in address space"
#error "Can't accommodate single IMSIC group in address space"
#endif
#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
VIRT_IMSIC_GROUP_MAX_SIZE)
#if 0x4000000 < VIRT_IMSIC_MAX_SIZE
#error "Can't accomodate all IMSIC groups in address space"
#error "Can't accommodate all IMSIC groups in address space"
#endif
static const MemMapEntry virt_memmap[] = {

2
include/hw/riscv/riscv_hart.h
View File

@ -3,7 +3,7 @@
*
* Copyright (c) 2017 SiFive, Inc.
*
* Holds the state of a heterogenous array of RISC-V harts
* Holds the state of a heterogeneous array of RISC-V harts
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,

2
target/riscv/cpu.h
View File

@ -349,7 +349,7 @@ struct CPUArchState {
target_ulong upmmask;
target_ulong upmbase;
/* CSRs for execution enviornment configuration */
/* CSRs for execution environment configuration */
uint64_t menvcfg;
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];

4
target/riscv/cpu_bits.h
View File

@ -656,7 +656,7 @@ typedef enum {
/* Leaf page shift amount */
#define PGSHIFT 12
/* Default Reset Vector adress */
/* Default Reset Vector address */
#define DEFAULT_RSTVEC 0x1000
/* Exception causes */
@ -740,7 +740,7 @@ typedef enum RISCVException {
#define PM_CURRENT 0x00000002ULL
#define PM_INSN 0x00000004ULL
/* Execution enviornment configuration bits */
/* Execution environment configuration bits */
#define MENVCFG_FIOM BIT(0)
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)

4
target/riscv/csr.c
View File

@ -3215,7 +3215,7 @@ static int write_hvipriox(CPURISCVState *env, int first_index,
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
/* Fill-up priority arrary */
/* Fill-up priority array */
for (i = 0; i < num_irqs; i++) {
if (riscv_cpu_hviprio_index2irq(first_index + i, &irq, &rdzero)) {
continue;
@ -3884,7 +3884,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
if (riscv_has_ext(env, RVH) && env->priv == PRV_S &&
!env->virt_enabled) {
/*
* We are in HS mode. Add 1 to the effective privledge level to
* We are in HS mode. Add 1 to the effective privilege level to
* allow us to access the Hypervisor CSRs.
*/
effective_priv++;

10
target/riscv/debug.c
View File

@ -574,7 +574,7 @@ static void riscv_itrigger_update_count(CPURISCVState *env)
int count, executed;
/*
* Record last icount, so that we can evaluate the executed instructions
* since last priviledge mode change or timer expire.
* since last privilege mode change or timer expire.
*/
int64_t last_icount = env->last_icount, current_icount;
current_icount = env->last_icount = icount_get_raw();
@ -588,14 +588,14 @@ static void riscv_itrigger_update_count(CPURISCVState *env)
continue;
}
/*
* Only when priviledge is changed or itrigger timer expires,
* Only when privilege is changed or itrigger timer expires,
* the count field in itrigger tdata1 register is updated.
* And the count field in itrigger only contains remaining value.
*/
if (check_itrigger_priv(env, i)) {
/*
* If itrigger enabled in this priviledge mode, the number of
* executed instructions since last priviledge change
* If itrigger enabled in this privilege mode, the number of
* executed instructions since last privilege change
* should be reduced from current itrigger count.
*/
executed = current_icount - last_icount;
@ -605,7 +605,7 @@ static void riscv_itrigger_update_count(CPURISCVState *env)
}
} else {
/*
* If itrigger is not enabled in this priviledge mode,
* If itrigger is not enabled in this privilege mode,
* the number of executed instructions will be discard and
* the count field in itrigger will not change.
*/

4
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -300,7 +300,7 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
tcg_gen_and_i64(dest, mask, rs1);
tcg_gen_or_i64(dest, dest, rs2);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
/* signed-extended instead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext32s_i64(dest, dest);
}
@ -345,7 +345,7 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(31, 1));
tcg_gen_xor_i64(dest, rs1, dest);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
/* signed-extended instead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext32s_i64(dest, dest);
}

4
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -2240,7 +2240,7 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)
*
* If SEW < FLEN, check whether input fp register is a valid
* NaN-boxed value, in which case the least-significant SEW bits
* of the f regsiter are used, else the canonical NaN value is used.
* of the f register are used, else the canonical NaN value is used.
*/
static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
{
@ -3282,7 +3282,7 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
}
}
/* offset of the idx element with base regsiter r */
/* offset of the idx element with base register r */
static uint32_t endian_ofs(DisasContext *s, int r, int idx)
{
#if HOST_BIG_ENDIAN

4
target/riscv/insn_trans/trans_rvzfh.c.inc
View File

@ -305,7 +305,7 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a)
tcg_gen_and_i64(dest, mask, rs1);
tcg_gen_or_i64(dest, dest, rs2);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
/* signed-extended instead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext16s_i64(dest, dest);
}
@ -349,7 +349,7 @@ static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnjx_h *a)
tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(15, 1));
tcg_gen_xor_i64(dest, rs1, dest);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
/* signed-extended instead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext16s_i64(dest, dest);
}

2
target/riscv/monitor.c
View File

@ -55,7 +55,7 @@ static void print_pte_header(Monitor *mon)
static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
hwaddr paddr, target_ulong size, int attr)
{
/* santity check on vaddr */
/* sanity check on vaddr */
if (vaddr >= (1UL << va_bits)) {
return;
}