hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR

For SSE-300, the SYSINFO register block has two new registers:

 * SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3;
   since the SSE-300 can only be configured with a single CPU it
   is always zero

 * IIDR is the subsystem implementation identity register;
   its value is set by the SoC integrator, so we plumb this in from
   the armsse.c code as we do with SYS_VERSION and SYS_CONFIG

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:45:43 +00:00
parent c89cef3a2c
commit 446587a914
3 changed files with 28 additions and 0 deletions

View File

@ -30,6 +30,7 @@ struct ARMSSEInfo {
int sram_banks; int sram_banks;
int num_cpus; int num_cpus;
uint32_t sys_version; uint32_t sys_version;
uint32_t iidr;
uint32_t cpuwait_rst; uint32_t cpuwait_rst;
bool has_mhus; bool has_mhus;
bool has_ppus; bool has_ppus;
@ -70,6 +71,7 @@ static const ARMSSEInfo armsse_variants[] = {
.sram_banks = 1, .sram_banks = 1,
.num_cpus = 1, .num_cpus = 1,
.sys_version = 0x41743, .sys_version = 0x41743,
.iidr = 0,
.cpuwait_rst = 0, .cpuwait_rst = 0,
.has_mhus = false, .has_mhus = false,
.has_ppus = false, .has_ppus = false,
@ -84,6 +86,7 @@ static const ARMSSEInfo armsse_variants[] = {
.sram_banks = 4, .sram_banks = 4,
.num_cpus = 2, .num_cpus = 2,
.sys_version = 0x22041743, .sys_version = 0x22041743,
.iidr = 0,
.cpuwait_rst = 2, .cpuwait_rst = 2,
.has_mhus = true, .has_mhus = true,
.has_ppus = true, .has_ppus = true,
@ -950,6 +953,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
} }
object_property_set_int(OBJECT(&s->sysinfo), "sse-version", object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
info->sse_version, &error_abort); info->sse_version, &error_abort);
object_property_set_int(OBJECT(&s->sysinfo), "IIDR",
info->iidr, &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) { if (!sysbus_realize(SYS_BUS_DEVICE(&s->sysinfo), errp)) {
return; return;
} }

View File

@ -30,6 +30,8 @@
REG32(SYS_VERSION, 0x0) REG32(SYS_VERSION, 0x0)
REG32(SYS_CONFIG, 0x4) REG32(SYS_CONFIG, 0x4)
REG32(SYS_CONFIG1, 0x8)
REG32(IIDR, 0xfc8)
REG32(PID4, 0xfd0) REG32(PID4, 0xfd0)
REG32(PID5, 0xfd4) REG32(PID5, 0xfd4)
REG32(PID6, 0xfd8) REG32(PID6, 0xfd8)
@ -70,6 +72,24 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset,
case A_SYS_CONFIG: case A_SYS_CONFIG:
r = s->sys_config; r = s->sys_config;
break; break;
case A_SYS_CONFIG1:
switch (s->sse_version) {
case ARMSSE_SSE300:
return 0;
break;
default:
goto bad_read;
}
break;
case A_IIDR:
switch (s->sse_version) {
case ARMSSE_SSE300:
return s->iidr;
break;
default:
goto bad_read;
}
break;
case A_PID4 ... A_CID3: case A_PID4 ... A_CID3:
switch (s->sse_version) { switch (s->sse_version) {
case ARMSSE_SSE300: case ARMSSE_SSE300:
@ -81,6 +101,7 @@ static uint64_t iotkit_sysinfo_read(void *opaque, hwaddr offset,
} }
break; break;
default: default:
bad_read:
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"IoTKit SysInfo read: bad offset %x\n", (int)offset); "IoTKit SysInfo read: bad offset %x\n", (int)offset);
r = 0; r = 0;
@ -114,6 +135,7 @@ static Property iotkit_sysinfo_props[] = {
DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0), DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysInfo, sys_version, 0),
DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0), DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0),
DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0), DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0),
DEFINE_PROP_UINT32("IIDR", IoTKitSysInfo, iidr, 0),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

View File

@ -39,6 +39,7 @@ struct IoTKitSysInfo {
uint32_t sys_version; uint32_t sys_version;
uint32_t sys_config; uint32_t sys_config;
uint32_t sse_version; uint32_t sse_version;
uint32_t iidr;
}; };
#endif #endif