target/arm: Move m_is_{ppb,system}_region to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-13-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -11677,21 +11677,6 @@ do_fault:
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return true;
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}
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bool m_is_ppb_region(CPUARMState *env, uint32_t address)
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{
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/* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
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return arm_feature(env, ARM_FEATURE_M) &&
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extract32(address, 20, 12) == 0xe00;
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}
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bool m_is_system_region(CPUARMState *env, uint32_t address)
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{
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/* True if address is in the M profile system region
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* 0xe0000000 - 0xffffffff
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*/
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return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
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}
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/* Combine either inner or outer cacheability attributes for normal
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* memory, according to table D4-42 and pseudocode procedure
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* CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
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@ -416,6 +416,22 @@ static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx,
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}
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}
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static bool m_is_ppb_region(CPUARMState *env, uint32_t address)
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{
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/* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
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return arm_feature(env, ARM_FEATURE_M) &&
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extract32(address, 20, 12) == 0xe00;
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}
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static bool m_is_system_region(CPUARMState *env, uint32_t address)
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{
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/*
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* True if address is in the M profile system region
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* 0xe0000000 - 0xffffffff
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*/
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return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
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}
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static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
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bool is_user)
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{
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@ -33,9 +33,6 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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bool m_is_ppb_region(CPUARMState *env, uint32_t address);
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bool m_is_system_region(CPUARMState *env, uint32_t address);
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bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0,
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