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target/riscv: Remove the hardcoded MSTATUS_SD macro 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-04-24 13:33:18 +10:00
parent 994b6bb2db
commit 4fd7455bb3
3 changed files with 27 additions and 14 deletions
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10
target/riscv/cpu_bits.h
View File

@ -368,16 +368,6 @@
#define MXL_RV64 2
#define MXL_RV128 3
#if defined(TARGET_RISCV32)
#define MSTATUS_SD MSTATUS32_SD
#define MISA_MXL MISA32_MXL
#define MXL_VAL MXL_RV32
#elif defined(TARGET_RISCV64)
#define MSTATUS_SD MSTATUS64_SD
#define MISA_MXL MISA64_MXL
#define MXL_VAL MXL_RV64
#endif
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002

12
target/riscv/csr.c
View File

@ -538,7 +538,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
if (riscv_cpu_is_32bit(env)) {
mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
} else {
mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
}
env->mstatus = mstatus;
return RISCV_EXCP_NONE;
@ -614,7 +618,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
}
/* misa.MXL writes are not supported by QEMU */
val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
if (riscv_cpu_is_32bit(env)) {
val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
} else {
val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
}
/* flush translation cache */
if (val != env->misa) {

19
target/riscv/translate.c
View File

@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
#ifdef TARGET_RISCV32
# define is_32bit(ctx) true
#elif defined(CONFIG_USER_ONLY)
# define is_32bit(ctx) false
#else
static inline bool is_32bit(DisasContext *ctx)
{
return (ctx->misa & RV32) == RV32;
}
#endif
/*
* RISC-V requires NaN-boxing of narrower width floating point values.
* This applies when a 32-bit value is assigned to a 64-bit FP register.
@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
target_ulong sd;
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
@ -376,13 +389,15 @@ static void mark_fs_dirty(DisasContext *ctx)
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new();
sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tmp);