- Added triboard with tc27x_soc
- Cleaned up get_physical_address() - Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK insns -----BEGIN PGP SIGNATURE----- iQJTBAABCgA9FiEEbmNqfoPy3Qz6bm43CtLGOWtpyhQFAmBOFUcfHGtiYXN0aWFu QG1haWwudW5pLXBhZGVyYm9ybi5kZQAKCRAK0sY5a2nKFNz/D/4va/Tz06aNPmDA Ep4aQDDfTFVjs16dgN4DAMUCuKD1pq2ot97uZL7B+B7nBsN+0UHErz0Mp1yT10Ae NbmSNJ7QFvDi5G8xHdZjCj2+Gs8hM4Ff0+kxnmFLqpGK5u8Pso0C3KapCHolwojb gk3WXFEeBYtEwBDkmUAbX/Lp018/bL+wbcf9sSfNcshUKmE3MAVCLNeMzJ3gqZOO H8yNVEM3sPoEecr8TayCaLoc8JQrQnHTc4tHT+jj078+HPyVpYRjr8PZkhm6Oh9i KzTjxKsQt5IPFXDLdKQj1KJeqtbQGm9GSIIi1cbLJBFalQT94qsgX46g29XNdz1A UqocKB1yZF+L/Fd+Ymxo1pNpL9nCuy9gMl1MNV7rmubufMzy/WEhWQfJvIBC9B+T PKs8TmR+HY/qe9mPZakUtaFx+Hh1QJ+HROtRKLovqUEvA76XRqAyDUAJNjkm68vB bimHN2YUOfVne4fvyigoLowdWMQ98B3v6Rh0r9wmAYuw9PR/SIkNIPHTRswz2MdK WkR21bOwklw96d5OgJM1aJ4mC7PGMFDkF4ErNp1/R8h16JDJ+kQMxxmaij2H19Oo cwe6qo7A+fgU6SsER5i75fn+eD0MQMK3UgGhwDhSw2/Kvhjlo+xhXnaI/a6wGFLl PIlT14oiRjR1082qiLl65i1bYTDryQ== =7YWJ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20210314' into staging - Added triboard with tc27x_soc - Cleaned up get_physical_address() - Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK insns # gpg: Signature made Sun 14 Mar 2021 13:53:11 GMT # gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14 # gpg: issuer "kbastian@mail.uni-paderborn.de" # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full] # Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14 * remotes/bkoppelmann2/tags/pull-tricore-20210314: target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 tricore: fixed faulty conditions for extr and imask target/tricore: Remove unused definitions target/tricore: Pass MMUAccessType to get_physical_address() target/tricore: Replace magic value by MMU_DATA_LOAD definition tricore: added triboard with tc27x_soc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
51204c2f18
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@ -1 +1 @@
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CONFIG_TRICORE=y
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CONFIG_TRIBOARD=y
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|
|
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|||
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@ -1,2 +1,10 @@
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config TRICORE
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bool
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config TRIBOARD
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bool
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select TRICORE
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select TC27X_SOC
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config TC27X_SOC
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bool
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|
|
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|||
|
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@ -1,4 +1,6 @@
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tricore_ss = ss.source_set()
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tricore_ss.add(when: 'CONFIG_TRICORE', if_true: files('tricore_testboard.c'))
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tricore_ss.add(when: 'CONFIG_TRIBOARD', if_true: files('triboard.c'))
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tricore_ss.add(when: 'CONFIG_TC27X_SOC', if_true: files('tc27x_soc.c'))
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hw_arch += {'tricore': tricore_ss}
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@ -0,0 +1,246 @@
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/*
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* Infineon tc27x SoC System emulation.
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*
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* Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
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* Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
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||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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||||
*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "qemu/units.h"
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#include "hw/misc/unimp.h"
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#include "exec/address-spaces.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/tricore/tc27x_soc.h"
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#include "hw/tricore/triboard.h"
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const MemmapEntry tc27x_soc_memmap[] = {
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[TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
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[TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
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[TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
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[TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
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[TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
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[TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
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[TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
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[TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
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[TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
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[TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
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[TC27XD_PCACHE1] = { 0x60108000, 16 * KiB },
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[TC27XD_PTAG1] = { 0x601C0000, 0x1800 },
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[TC27XD_DSPR0] = { 0x70000000, 112 * KiB },
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[TC27XD_PSPR0] = { 0x70100000, 24 * KiB },
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[TC27XD_PCACHE0] = { 0x70106000, 8 * KiB },
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[TC27XD_PTAG0] = { 0x701C0000, 0xC00 },
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[TC27XD_PFLASH0_C] = { 0x80000000, 2 * MiB },
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[TC27XD_PFLASH1_C] = { 0x80200000, 2 * MiB },
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[TC27XD_OLDA_C] = { 0x8FE70000, 32 * KiB },
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[TC27XD_BROM_C] = { 0x8FFF8000, 32 * KiB },
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[TC27XD_LMURAM_C] = { 0x90000000, 32 * KiB },
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[TC27XD_EMEM_C] = { 0x9F000000, 1 * MiB },
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[TC27XD_PFLASH0_U] = { 0xA0000000, 0x0 },
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[TC27XD_PFLASH1_U] = { 0xA0200000, 0x0 },
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[TC27XD_DFLASH0] = { 0xAF000000, 1 * MiB + 16 * KiB },
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[TC27XD_DFLASH1] = { 0xAF110000, 64 * KiB },
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[TC27XD_OLDA_U] = { 0xAFE70000, 0x0 },
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[TC27XD_BROM_U] = { 0xAFFF8000, 0x0 },
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[TC27XD_LMURAM_U] = { 0xB0000000, 0x0 },
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[TC27XD_EMEM_U] = { 0xBF000000, 0x0 },
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[TC27XD_PSPRX] = { 0xC0000000, 0x0 },
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[TC27XD_DSPRX] = { 0xD0000000, 0x0 },
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};
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/*
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* Initialize the auxiliary ROM region @mr and map it into
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* the memory map at @base.
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*/
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static void make_rom(MemoryRegion *mr, const char *name,
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hwaddr base, hwaddr size)
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{
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memory_region_init_rom(mr, NULL, name, size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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/*
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* Initialize the auxiliary RAM region @mr and map it into
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* the memory map at @base.
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*/
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static void make_ram(MemoryRegion *mr, const char *name,
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hwaddr base, hwaddr size)
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{
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memory_region_init_ram(mr, NULL, name, size, &error_fatal);
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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/*
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* Create an alias of an entire original MemoryRegion @orig
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* located at @base in the memory map.
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*/
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static void make_alias(MemoryRegion *mr, const char *name,
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MemoryRegion *orig, hwaddr base)
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{
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memory_region_init_alias(mr, NULL, name, orig, 0,
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memory_region_size(orig));
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memory_region_add_subregion(get_system_memory(), base, mr);
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}
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static void tc27x_soc_init_memory_mapping(DeviceState *dev_soc)
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{
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TC27XSoCState *s = TC27X_SOC(dev_soc);
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TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
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make_ram(&s->cpu0mem.dspr, "CPU0.DSPR",
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sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size);
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make_ram(&s->cpu0mem.pspr, "CPU0.PSPR",
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sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size);
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make_ram(&s->cpu1mem.dspr, "CPU1.DSPR",
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sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size);
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make_ram(&s->cpu1mem.pspr, "CPU1.PSPR",
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sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size);
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make_ram(&s->cpu2mem.dspr, "CPU2.DSPR",
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sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size);
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make_ram(&s->cpu2mem.pspr, "CPU2.PSPR",
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sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size);
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||||
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/* TODO: Control Cache mapping with Memory Test Unit (MTU) */
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make_ram(&s->cpu2mem.dcache, "CPU2.DCACHE",
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sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size);
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make_ram(&s->cpu2mem.dtag, "CPU2.DTAG",
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sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size);
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make_ram(&s->cpu2mem.pcache, "CPU2.PCACHE",
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sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size);
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make_ram(&s->cpu2mem.ptag, "CPU2.PTAG",
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sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size);
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make_ram(&s->cpu1mem.dcache, "CPU1.DCACHE",
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sc->memmap[TC27XD_DCACHE1].base, sc->memmap[TC27XD_DCACHE1].size);
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make_ram(&s->cpu1mem.dtag, "CPU1.DTAG",
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sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size);
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make_ram(&s->cpu1mem.pcache, "CPU1.PCACHE",
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sc->memmap[TC27XD_PCACHE1].base, sc->memmap[TC27XD_PCACHE1].size);
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make_ram(&s->cpu1mem.ptag, "CPU1.PTAG",
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sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size);
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make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE",
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sc->memmap[TC27XD_PCACHE0].base, sc->memmap[TC27XD_PCACHE0].size);
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make_ram(&s->cpu0mem.ptag, "CPU0.PTAG",
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sc->memmap[TC27XD_PTAG0].base, sc->memmap[TC27XD_PTAG0].size);
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||||
|
||||
/*
|
||||
* TriCore QEMU executes CPU0 only, thus it is sufficient to map
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* LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
|
||||
*/
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||||
make_alias(&s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr,
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sc->memmap[TC27XD_PSPRX].base);
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make_alias(&s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr,
|
||||
sc->memmap[TC27XD_DSPRX].base);
|
||||
|
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make_ram(&s->flashmem.pflash0_c, "PF0",
|
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sc->memmap[TC27XD_PFLASH0_C].base, sc->memmap[TC27XD_PFLASH0_C].size);
|
||||
make_ram(&s->flashmem.pflash1_c, "PF1",
|
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sc->memmap[TC27XD_PFLASH1_C].base, sc->memmap[TC27XD_PFLASH1_C].size);
|
||||
make_ram(&s->flashmem.dflash0, "DF0",
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sc->memmap[TC27XD_DFLASH0].base, sc->memmap[TC27XD_DFLASH0].size);
|
||||
make_ram(&s->flashmem.dflash1, "DF1",
|
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sc->memmap[TC27XD_DFLASH1].base, sc->memmap[TC27XD_DFLASH1].size);
|
||||
make_ram(&s->flashmem.olda_c, "OLDA",
|
||||
sc->memmap[TC27XD_OLDA_C].base, sc->memmap[TC27XD_OLDA_C].size);
|
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make_rom(&s->flashmem.brom_c, "BROM",
|
||||
sc->memmap[TC27XD_BROM_C].base, sc->memmap[TC27XD_BROM_C].size);
|
||||
make_ram(&s->flashmem.lmuram_c, "LMURAM",
|
||||
sc->memmap[TC27XD_LMURAM_C].base, sc->memmap[TC27XD_LMURAM_C].size);
|
||||
make_ram(&s->flashmem.emem_c, "EMEM",
|
||||
sc->memmap[TC27XD_EMEM_C].base, sc->memmap[TC27XD_EMEM_C].size);
|
||||
|
||||
make_alias(&s->flashmem.pflash0_u, "PF0.U", &s->flashmem.pflash0_c,
|
||||
sc->memmap[TC27XD_PFLASH0_U].base);
|
||||
make_alias(&s->flashmem.pflash1_u, "PF1.U", &s->flashmem.pflash1_c,
|
||||
sc->memmap[TC27XD_PFLASH1_U].base);
|
||||
make_alias(&s->flashmem.olda_u, "OLDA.U", &s->flashmem.olda_c,
|
||||
sc->memmap[TC27XD_OLDA_U].base);
|
||||
make_alias(&s->flashmem.brom_u, "BROM.U", &s->flashmem.brom_c,
|
||||
sc->memmap[TC27XD_BROM_U].base);
|
||||
make_alias(&s->flashmem.lmuram_u, "LMURAM.U", &s->flashmem.lmuram_c,
|
||||
sc->memmap[TC27XD_LMURAM_U].base);
|
||||
make_alias(&s->flashmem.emem_u, "EMEM.U", &s->flashmem.emem_c,
|
||||
sc->memmap[TC27XD_EMEM_U].base);
|
||||
}
|
||||
|
||||
static void tc27x_soc_realize(DeviceState *dev_soc, Error **errp)
|
||||
{
|
||||
TC27XSoCState *s = TC27X_SOC(dev_soc);
|
||||
Error *err = NULL;
|
||||
|
||||
qdev_realize(DEVICE(&s->cpu), NULL, &err);
|
||||
if (err) {
|
||||
error_propagate(errp, err);
|
||||
return;
|
||||
}
|
||||
|
||||
tc27x_soc_init_memory_mapping(dev_soc);
|
||||
}
|
||||
|
||||
static void tc27x_soc_init(Object *obj)
|
||||
{
|
||||
TC27XSoCState *s = TC27X_SOC(obj);
|
||||
TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
|
||||
|
||||
object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type);
|
||||
}
|
||||
|
||||
static Property tc27x_soc_properties[] = {
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void tc27x_soc_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
|
||||
dc->realize = tc27x_soc_realize;
|
||||
device_class_set_props(dc, tc27x_soc_properties);
|
||||
}
|
||||
|
||||
static void tc277d_soc_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
TC27XSoCClass *sc = TC27X_SOC_CLASS(oc);
|
||||
|
||||
sc->name = "tc277d-soc";
|
||||
sc->cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
|
||||
sc->memmap = tc27x_soc_memmap;
|
||||
sc->num_cpus = 1;
|
||||
}
|
||||
|
||||
static const TypeInfo tc27x_soc_types[] = {
|
||||
{
|
||||
.name = "tc277d-soc",
|
||||
.parent = TYPE_TC27X_SOC,
|
||||
.class_init = tc277d_soc_class_init,
|
||||
}, {
|
||||
.name = TYPE_TC27X_SOC,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(TC27XSoCState),
|
||||
.instance_init = tc27x_soc_init,
|
||||
.class_size = sizeof(TC27XSoCClass),
|
||||
.class_init = tc27x_soc_class_init,
|
||||
.abstract = true,
|
||||
},
|
||||
};
|
||||
|
||||
DEFINE_TYPES(tc27x_soc_types)
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Infineon TriBoard System emulation.
|
||||
*
|
||||
* Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
|
||||
* Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/units.h"
|
||||
#include "qapi/error.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "cpu.h"
|
||||
#include "net/net.h"
|
||||
#include "hw/boards.h"
|
||||
#include "hw/loader.h"
|
||||
#include "exec/address-spaces.h"
|
||||
#include "elf.h"
|
||||
#include "hw/tricore/tricore.h"
|
||||
#include "qemu/error-report.h"
|
||||
|
||||
#include "hw/tricore/triboard.h"
|
||||
#include "hw/tricore/tc27x_soc.h"
|
||||
|
||||
static void tricore_load_kernel(const char *kernel_filename)
|
||||
{
|
||||
uint64_t entry;
|
||||
long kernel_size;
|
||||
TriCoreCPU *cpu;
|
||||
CPUTriCoreState *env;
|
||||
|
||||
kernel_size = load_elf(kernel_filename, NULL,
|
||||
NULL, NULL, &entry, NULL,
|
||||
NULL, NULL, 0,
|
||||
EM_TRICORE, 1, 0);
|
||||
if (kernel_size <= 0) {
|
||||
error_report("no kernel file '%s'", kernel_filename);
|
||||
exit(1);
|
||||
}
|
||||
cpu = TRICORE_CPU(first_cpu);
|
||||
env = &cpu->env;
|
||||
env->PC = entry;
|
||||
}
|
||||
|
||||
|
||||
static void triboard_machine_init(MachineState *machine)
|
||||
{
|
||||
TriBoardMachineState *ms = TRIBOARD_MACHINE(machine);
|
||||
TriBoardMachineClass *amc = TRIBOARD_MACHINE_GET_CLASS(machine);
|
||||
|
||||
object_initialize_child(OBJECT(machine), "soc", &ms->tc27x_soc,
|
||||
amc->soc_name);
|
||||
sysbus_realize(SYS_BUS_DEVICE(&ms->tc27x_soc), &error_fatal);
|
||||
|
||||
if (machine->kernel_filename) {
|
||||
tricore_load_kernel(machine->kernel_filename);
|
||||
}
|
||||
}
|
||||
|
||||
static void triboard_machine_tc277d_class_init(ObjectClass *oc,
|
||||
void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
TriBoardMachineClass *amc = TRIBOARD_MACHINE_CLASS(oc);
|
||||
|
||||
mc->init = triboard_machine_init;
|
||||
mc->desc = "Infineon AURIX TriBoard TC277 (D-Step)";
|
||||
mc->max_cpus = 1;
|
||||
amc->soc_name = "tc277d-soc";
|
||||
};
|
||||
|
||||
static const TypeInfo triboard_machine_types[] = {
|
||||
{
|
||||
.name = MACHINE_TYPE_NAME("KIT_AURIX_TC277_TRB"),
|
||||
.parent = TYPE_TRIBOARD_MACHINE,
|
||||
.class_init = triboard_machine_tc277d_class_init,
|
||||
}, {
|
||||
.name = TYPE_TRIBOARD_MACHINE,
|
||||
.parent = TYPE_MACHINE,
|
||||
.instance_size = sizeof(TriBoardMachineState),
|
||||
.class_size = sizeof(TriBoardMachineClass),
|
||||
.abstract = true,
|
||||
},
|
||||
};
|
||||
|
||||
DEFINE_TYPES(triboard_machine_types)
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/*
|
||||
* Infineon tc27x SoC System emulation.
|
||||
*
|
||||
* Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
|
||||
* Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef TC27X_SoC_H
|
||||
#define TC27X_SoC_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "target/tricore/cpu.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_TC27X_SOC ("tc27x-soc")
|
||||
OBJECT_DECLARE_TYPE(TC27XSoCState, TC27XSoCClass, TC27X_SOC)
|
||||
|
||||
typedef struct TC27XSoCCPUMemState {
|
||||
|
||||
MemoryRegion dspr;
|
||||
MemoryRegion pspr;
|
||||
|
||||
MemoryRegion dcache;
|
||||
MemoryRegion dtag;
|
||||
MemoryRegion pcache;
|
||||
MemoryRegion ptag;
|
||||
|
||||
} TC27XSoCCPUMemState;
|
||||
|
||||
typedef struct TC27XSoCFlashMemState {
|
||||
|
||||
MemoryRegion pflash0_c;
|
||||
MemoryRegion pflash1_c;
|
||||
MemoryRegion pflash0_u;
|
||||
MemoryRegion pflash1_u;
|
||||
MemoryRegion dflash0;
|
||||
MemoryRegion dflash1;
|
||||
MemoryRegion olda_c;
|
||||
MemoryRegion olda_u;
|
||||
MemoryRegion brom_c;
|
||||
MemoryRegion brom_u;
|
||||
MemoryRegion lmuram_c;
|
||||
MemoryRegion lmuram_u;
|
||||
MemoryRegion emem_c;
|
||||
MemoryRegion emem_u;
|
||||
|
||||
} TC27XSoCFlashMemState;
|
||||
|
||||
typedef struct TC27XSoCState {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/*< public >*/
|
||||
TriCoreCPU cpu;
|
||||
|
||||
MemoryRegion dsprX;
|
||||
MemoryRegion psprX;
|
||||
|
||||
TC27XSoCCPUMemState cpu0mem;
|
||||
TC27XSoCCPUMemState cpu1mem;
|
||||
TC27XSoCCPUMemState cpu2mem;
|
||||
|
||||
TC27XSoCFlashMemState flashmem;
|
||||
|
||||
} TC27XSoCState;
|
||||
|
||||
typedef struct MemmapEntry {
|
||||
hwaddr base;
|
||||
hwaddr size;
|
||||
} MemmapEntry;
|
||||
|
||||
typedef struct TC27XSoCClass {
|
||||
DeviceClass parent_class;
|
||||
|
||||
const char *name;
|
||||
const char *cpu_type;
|
||||
const MemmapEntry *memmap;
|
||||
uint32_t num_cpus;
|
||||
} TC27XSoCClass;
|
||||
|
||||
enum {
|
||||
TC27XD_DSPR2,
|
||||
TC27XD_DCACHE2,
|
||||
TC27XD_DTAG2,
|
||||
TC27XD_PSPR2,
|
||||
TC27XD_PCACHE2,
|
||||
TC27XD_PTAG2,
|
||||
TC27XD_DSPR1,
|
||||
TC27XD_DCACHE1,
|
||||
TC27XD_DTAG1,
|
||||
TC27XD_PSPR1,
|
||||
TC27XD_PCACHE1,
|
||||
TC27XD_PTAG1,
|
||||
TC27XD_DSPR0,
|
||||
TC27XD_PSPR0,
|
||||
TC27XD_PCACHE0,
|
||||
TC27XD_PTAG0,
|
||||
TC27XD_PFLASH0_C,
|
||||
TC27XD_PFLASH1_C,
|
||||
TC27XD_OLDA_C,
|
||||
TC27XD_BROM_C,
|
||||
TC27XD_LMURAM_C,
|
||||
TC27XD_EMEM_C,
|
||||
TC27XD_PFLASH0_U,
|
||||
TC27XD_PFLASH1_U,
|
||||
TC27XD_DFLASH0,
|
||||
TC27XD_DFLASH1,
|
||||
TC27XD_OLDA_U,
|
||||
TC27XD_BROM_U,
|
||||
TC27XD_LMURAM_U,
|
||||
TC27XD_EMEM_U,
|
||||
TC27XD_PSPRX,
|
||||
TC27XD_DSPRX,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Infineon TriBoard System emulation.
|
||||
*
|
||||
* Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
|
||||
* Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qapi/error.h"
|
||||
#include "hw/boards.h"
|
||||
#include "hw/arm/boot.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "exec/address-spaces.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#include "hw/tricore/tc27x_soc.h"
|
||||
|
||||
#define TYPE_TRIBOARD_MACHINE MACHINE_TYPE_NAME("triboard")
|
||||
typedef struct TriBoardMachineState TriBoardMachineState;
|
||||
typedef struct TriBoardMachineClass TriBoardMachineClass;
|
||||
DECLARE_OBJ_CHECKERS(TriBoardMachineState, TriBoardMachineClass,
|
||||
TRIBOARD_MACHINE, TYPE_TRIBOARD_MACHINE)
|
||||
|
||||
|
||||
struct TriBoardMachineState {
|
||||
MachineState parent;
|
||||
|
||||
TC27XSoCState tc27x_soc;
|
||||
};
|
||||
|
||||
struct TriBoardMachineClass {
|
||||
MachineClass parent_obj;
|
||||
|
||||
const char *name;
|
||||
const char *desc;
|
||||
const char *soc_name;
|
||||
};
|
||||
|
|
@ -375,18 +375,6 @@ typedef TriCoreCPU ArchCPU;
|
|||
|
||||
#include "exec/cpu-all.h"
|
||||
|
||||
enum {
|
||||
/* 1 bit to define user level / supervisor access */
|
||||
ACCESS_USER = 0x00,
|
||||
ACCESS_SUPER = 0x01,
|
||||
/* 1 bit to indicate direction */
|
||||
ACCESS_STORE = 0x02,
|
||||
/* Type of instruction that generated the access */
|
||||
ACCESS_CODE = 0x10, /* Code fetch access */
|
||||
ACCESS_INT = 0x20, /* Integer load/store access */
|
||||
ACCESS_FLOAT = 0x30, /* floating point load/store access */
|
||||
};
|
||||
|
||||
void cpu_state_reset(CPUTriCoreState *s);
|
||||
void tricore_tcg_init(void);
|
||||
int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ enum {
|
|||
#if defined(CONFIG_SOFTMMU)
|
||||
static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
|
||||
int *prot, target_ulong address,
|
||||
int rw, int access_type)
|
||||
MMUAccessType access_type, int mmu_idx)
|
||||
{
|
||||
int ret = TLBRET_MATCH;
|
||||
|
||||
|
|
@ -50,7 +50,8 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
|||
int prot;
|
||||
int mmu_idx = cpu_mmu_index(&cpu->env, false);
|
||||
|
||||
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
|
||||
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr,
|
||||
MMU_DATA_LOAD, mmu_idx)) {
|
||||
return -1;
|
||||
}
|
||||
return phys_addr;
|
||||
|
|
@ -71,13 +72,11 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|||
CPUTriCoreState *env = &cpu->env;
|
||||
hwaddr physical;
|
||||
int prot;
|
||||
int access_type;
|
||||
int ret = 0;
|
||||
|
||||
rw &= 1;
|
||||
access_type = ACCESS_INT;
|
||||
ret = get_physical_address(env, &physical, &prot,
|
||||
address, rw, access_type);
|
||||
address, rw, mmu_idx);
|
||||
|
||||
qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical "
|
||||
TARGET_FMT_plx " prot %d\n",
|
||||
|
|
|
|||
|
|
@ -5777,8 +5777,8 @@ static void decode_rcpw_insert(DisasContext *ctx)
|
|||
switch (op2) {
|
||||
case OPC2_32_RCPW_IMASK:
|
||||
CHECK_REG_PAIR(r2);
|
||||
/* if pos + width > 31 undefined result */
|
||||
if (pos + width <= 31) {
|
||||
/* if pos + width > 32 undefined result */
|
||||
if (pos + width <= 32) {
|
||||
tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
|
||||
tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
|
||||
}
|
||||
|
|
@ -6989,6 +6989,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
|
|||
uint32_t op2;
|
||||
int r1, r2, r3;
|
||||
int32_t pos, width;
|
||||
TCGv temp;
|
||||
|
||||
op2 = MASK_OP_RRPW_OP2(ctx->opcode);
|
||||
r1 = MASK_OP_RRPW_S1(ctx->opcode);
|
||||
|
|
@ -6999,7 +7000,12 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
|
|||
|
||||
switch (op2) {
|
||||
case OPC2_32_RRPW_EXTR:
|
||||
if (pos + width <= 31) {
|
||||
if (width == 0) {
|
||||
tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
|
||||
break;
|
||||
}
|
||||
|
||||
if (pos + width <= 32) {
|
||||
/* optimize special cases */
|
||||
if ((pos == 0) && (width == 8)) {
|
||||
tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
|
||||
|
|
@ -7021,10 +7027,15 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
|
|||
break;
|
||||
case OPC2_32_RRPW_IMASK:
|
||||
CHECK_REG_PAIR(r3);
|
||||
if (pos + width <= 31) {
|
||||
tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
|
||||
|
||||
if (pos + width <= 32) {
|
||||
temp = tcg_temp_new();
|
||||
tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos);
|
||||
tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
|
||||
tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp);
|
||||
tcg_temp_free(temp);
|
||||
}
|
||||
|
||||
break;
|
||||
case OPC2_32_RRPW_INSERT:
|
||||
if (pos + width <= 32) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue