* target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()
* hw/arm: do not free machine->fdt in arm_load_dtb() * target/arm: Fix generated code for cpreg reads when HSTR is active * hw/ssi: Fix Linux driver init issue with xilinx_spi -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmQq+CwZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ux4EACRzqDTA3bbmuEDC4HKFEwv p4IrhG20iZWOQaieu7B+nrhXYakkcLxtGqG0cLFbb073B16SWRAxwli1sH+5mBNW l7GEF8WUelSPLZUlPmfl4YGH2ak5+kXI/G92+X7uE76Bv6wOJYZC5S1iNZN67fcd fQEfb9IcSmytCvsQLfLCvYzgpJKTuuikzkoCnT9O43qpPmUsBhSsBzyYPu0ZqsjV OgFMGNUc80rHc1kcLoLMMJBzI5S+iurnDKD+aNkMzCjtKPGkuIljbE6fPANXFxLb KbpVYjVIpPBAC33ZGO8NTkzqBuO7VNY0xWstfmepAsOdrorTLAOVMnC2NPsSZzOz kLd2wTT+64eMxt+flZETuU6HF8f6K94GRWPw8dC7Aj3XUvbSso+in863XD2OIKAr MCEm2Xi8ogb14uNx9Z4pUFIU6gKNUx8OGnWPLBngF4Kix4yP56nkbRAlg2ZII5bH HBny6+llC1NB94MjfSorTnNkk6J8Kd4Zhw8C9+dNbaDxCUBz3oCFwLoq6Cgx97F6 4J4An4PGF4evrJWBo9+9qOKtKapXlEmCSYs7oVavabxCCLI92PVoz96QH+6OK7+c h0PiqlfjPPSCnUcxsA9mr8zbp+P/ZxJbh0YI9ExP+zI03wE8gr4NMf7HYZQh0OLU Q+HARsmaAG3FONWbnHE97A== =oIZg -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm into staging * target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() * hw/arm: do not free machine->fdt in arm_load_dtb() * target/arm: Fix generated code for cpreg reads when HSTR is active * hw/ssi: Fix Linux driver init issue with xilinx_spi # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmQq+CwZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3ux4EACRzqDTA3bbmuEDC4HKFEwv # p4IrhG20iZWOQaieu7B+nrhXYakkcLxtGqG0cLFbb073B16SWRAxwli1sH+5mBNW # l7GEF8WUelSPLZUlPmfl4YGH2ak5+kXI/G92+X7uE76Bv6wOJYZC5S1iNZN67fcd # fQEfb9IcSmytCvsQLfLCvYzgpJKTuuikzkoCnT9O43qpPmUsBhSsBzyYPu0ZqsjV # OgFMGNUc80rHc1kcLoLMMJBzI5S+iurnDKD+aNkMzCjtKPGkuIljbE6fPANXFxLb # KbpVYjVIpPBAC33ZGO8NTkzqBuO7VNY0xWstfmepAsOdrorTLAOVMnC2NPsSZzOz # kLd2wTT+64eMxt+flZETuU6HF8f6K94GRWPw8dC7Aj3XUvbSso+in863XD2OIKAr # MCEm2Xi8ogb14uNx9Z4pUFIU6gKNUx8OGnWPLBngF4Kix4yP56nkbRAlg2ZII5bH # HBny6+llC1NB94MjfSorTnNkk6J8Kd4Zhw8C9+dNbaDxCUBz3oCFwLoq6Cgx97F6 # 4J4An4PGF4evrJWBo9+9qOKtKapXlEmCSYs7oVavabxCCLI92PVoz96QH+6OK7+c # h0PiqlfjPPSCnUcxsA9mr8zbp+P/ZxJbh0YI9ExP+zI03wE8gr4NMf7HYZQh0OLU # Q+HARsmaAG3FONWbnHE97A== # =oIZg # -----END PGP SIGNATURE----- # gpg: Signature made Mon 03 Apr 2023 17:00:44 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230403' of https://git.linaro.org/people/pmaydell/qemu-arm: hw/ssi: Fix Linux driver init issue with xilinx_spi target/arm: Fix generated code for cpreg reads when HSTR is active hw/arm: do not free machine->fdt in arm_load_dtb() target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
51a6dc9d39
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@ -689,7 +689,10 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
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qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
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rom_ptr_for_as(as, addr, size));
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g_free(fdt);
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if (fdt != ms->fdt) {
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g_free(ms->fdt);
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ms->fdt = fdt;
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}
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return size;
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@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s)
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txfifo_reset(s);
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s->regs[R_SPISSR] = ~0;
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s->regs[R_SPICR] = R_SPICR_MTI;
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xlx_spi_update_irq(s);
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xlx_spi_update_cs(s);
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}
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@ -230,8 +230,11 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
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{
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bool is_data = !(reg & 1);
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bool is_high = reg & 2;
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uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
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return gdb_get_reg64(buf, mask);
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ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
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ARMVAParameters param;
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param = aa64_va_parameters(env, -is_high, mmu_idx, is_data);
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return gdb_get_reg64(buf, pauth_ptr_mask(param));
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}
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default:
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return 0;
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@ -1391,13 +1391,18 @@ bool arm_generate_debug_exceptions(CPUARMState *env);
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/**
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* pauth_ptr_mask:
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* @env: cpu context
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* @ptr: selects between TTBR0 and TTBR1
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* @data: selects between TBI and TBID
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* @param: parameters defining the MMU setup
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*
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* Return a mask of the bits of @ptr that contain the authentication code.
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* Return a mask of the address bits that contain the authentication code,
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* given the MMU config defined by @param.
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*/
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uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
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static inline uint64_t pauth_ptr_mask(ARMVAParameters param)
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{
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int bot_pac_bit = 64 - param.tsz;
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int top_pac_bit = 64 - 8 * param.tbi;
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return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
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}
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/* Add the cpreg definitions for debug related system registers */
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void define_debug_regs(ARMCPU *cpu);
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@ -339,17 +339,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
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return pac | ext | ptr;
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}
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static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
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{
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int bot_pac_bit = 64 - param.tsz;
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int top_pac_bit = 64 - 8 * param.tbi;
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return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
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}
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static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
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{
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uint64_t mask = pauth_ptr_mask_internal(param);
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uint64_t mask = pauth_ptr_mask(param);
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/* Note that bit 55 is used whether or not the regime has 2 ranges. */
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if (extract64(ptr, 55, 1)) {
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@ -359,14 +351,6 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
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}
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}
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uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
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{
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ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
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ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
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return pauth_ptr_mask_internal(param);
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}
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static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
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ARMPACKey *key, bool data, int keynumber)
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{
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@ -4623,6 +4623,12 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
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gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
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/*
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* gen_exception_insn() will set is_jmp to DISAS_NORETURN,
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* but since we're conditionally branching over it, we want
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* to assume continue-to-next-instruction.
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*/
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s->base.is_jmp = DISAS_NEXT;
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set_disas_label(s, over);
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}
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}
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