usb: bugfixes for hid and xhci.

-----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmCw/H8ACgkQTLbY7tPo
 cThFEg//RtFvPLdiPK5/jxNSM+4nQURNAVmVgU737bHbrERlDJeCVS1tiqj9fHJb
 jNO06meX0tFwme5ExjdIQa4jG4Am/fNByGVb0PZqlqG3IhHdwjLOHy1fInhlEyIp
 15EgY/6C24hOVY9UHiAExTicyKqvrMcgEPJ3XSlbD8RiAP5hVjB8rejlDNz1tq+/
 pL5IfS+JV/GUPd/Pekkgy4t+HRvTKGHMSNLHAmsZrSqNhLdPArWgdipVtF52df69
 Omg27HrxZq8WbrVuVsC4N2sMieRO5MkeJZumlNerENS08MB4wkwpSSJCgEdNXu3m
 bIbOvFcAYiKRpHXHrgrDpNeJh6feG+lLGtNywq405ND0ahkH5ybBxTwahZI5imHW
 4SccEBvuY+pzPhP7sUm2N1mZlLX6N49yjbS5wT8TGaV2HgmVQEm68dYhLaLI5KXk
 vvgwn0PV3zShPEp3irOUKuRWFfSJ6Bg5/oMAhwb7qgES/gKxZUzeMjSynuOiwJs0
 mj/0vRj9N2lvZU4NxAdrShgxHMhoB7uqEDOv0lb8qIGYwG7meAelaObh++zG+9nG
 ELMraWfZBwllBAiSVmRl/72dVqAl9IQe0X6+Vbdx4s3LmUaBfgiL2niZyvnw246O
 ERD7mgs00szvAqf8tl6juWFeGj7MbWSlnFRw/4xtZ+0twI29KjY=
 =Gk/k
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210528-pull-request' into staging

usb: bugfixes for hid and xhci.

# gpg: Signature made Fri 28 May 2021 15:21:51 BST
# gpg:                using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/usb-20210528-pull-request:
  hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X
  hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to
  hw/input/hid: Add support for keys of jp106 keyboard.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-05-30 20:10:30 +01:00
commit 52848929b7
5 changed files with 20 additions and 11 deletions

View File

@ -51,8 +51,8 @@ static const uint8_t hid_usage_keys[0x100] = {
0x45, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x45, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
0xe8, 0xe9, 0x71, 0x72, 0x73, 0x00, 0x00, 0x00, 0xe8, 0xe9, 0x71, 0x72, 0x73, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x87, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0xe3, 0xe7, 0x65, 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x89, 0xe7, 0x65,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

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@ -57,7 +57,7 @@ static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
} }
} }
static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
{ {
XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
PCIDevice *pci_dev = PCI_DEVICE(s); PCIDevice *pci_dev = PCI_DEVICE(s);
@ -67,15 +67,18 @@ static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
msi_enabled(pci_dev))) { msi_enabled(pci_dev))) {
pci_set_irq(pci_dev, level); pci_set_irq(pci_dev, level);
} }
if (msix_enabled(pci_dev)) {
if (msix_enabled(pci_dev) && level) {
msix_notify(pci_dev, n); msix_notify(pci_dev, n);
return; return true;
} }
if (msi_enabled(pci_dev)) { if (msi_enabled(pci_dev) && level) {
msi_notify(pci_dev, n); msi_notify(pci_dev, n);
return; return true;
} }
return false;
} }
static void xhci_pci_reset(DeviceState *dev) static void xhci_pci_reset(DeviceState *dev)

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@ -16,11 +16,13 @@
#include "hw/acpi/aml-build.h" #include "hw/acpi/aml-build.h"
#include "hw/irq.h" #include "hw/irq.h"
static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level) static bool xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
{ {
XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci); XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
qemu_set_irq(s->irq[n], level); qemu_set_irq(s->irq[n], level);
return false;
} }
void xhci_sysbus_reset(DeviceState *dev) void xhci_sysbus_reset(DeviceState *dev)

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@ -551,7 +551,9 @@ static void xhci_intr_update(XHCIState *xhci, int v)
level = 1; level = 1;
} }
if (xhci->intr_raise) { if (xhci->intr_raise) {
xhci->intr_raise(xhci, 0, level); if (xhci->intr_raise(xhci, 0, level)) {
xhci->intr[0].iman &= ~IMAN_IP;
}
} }
} }
if (xhci->intr_update) { if (xhci->intr_update) {
@ -579,7 +581,9 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
return; return;
} }
if (xhci->intr_raise) { if (xhci->intr_raise) {
xhci->intr_raise(xhci, v, true); if (xhci->intr_raise(xhci, v, true)) {
xhci->intr[v].iman &= ~IMAN_IP;
}
} }
} }

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@ -194,7 +194,7 @@ typedef struct XHCIState {
uint32_t flags; uint32_t flags;
uint32_t max_pstreams_mask; uint32_t max_pstreams_mask;
void (*intr_update)(XHCIState *s, int n, bool enable); void (*intr_update)(XHCIState *s, int n, bool enable);
void (*intr_raise)(XHCIState *s, int n, bool level); bool (*intr_raise)(XHCIState *s, int n, bool level);
DeviceState *hostOpaque; DeviceState *hostOpaque;
/* Operational Registers */ /* Operational Registers */