target/riscv: Drop temp_new
Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new. Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -51,7 +51,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
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decode_save_opc(ctx);
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decode_save_opc(ctx);
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t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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t0 = get_gpr(ctx, a->rs1, EXT_NONE);
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if (a->imm) {
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if (a->imm) {
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TCGv temp = temp_new(ctx);
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TCGv temp = tcg_temp_new();
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tcg_gen_addi_tl(temp, t0, a->imm);
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tcg_gen_addi_tl(temp, t0, a->imm);
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t0 = temp;
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t0 = temp;
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}
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}
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@ -101,11 +101,8 @@ typedef struct DisasContext {
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bool cfg_vta_all_1s;
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bool cfg_vta_all_1s;
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target_ulong vstart;
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target_ulong vstart;
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bool vl_eq_vlmax;
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bool vl_eq_vlmax;
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uint8_t ntemp;
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CPUState *cs;
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CPUState *cs;
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TCGv zero;
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TCGv zero;
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/* Space for 3 operands plus 1 extra for address computation. */
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TCGv temp[4];
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/* PointerMasking extension */
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/* PointerMasking extension */
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bool pm_mask_enabled;
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bool pm_mask_enabled;
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bool pm_base_enabled;
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bool pm_base_enabled;
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@ -312,12 +309,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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*
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*
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* Further, we may provide an extension for word operations.
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* Further, we may provide an extension for word operations.
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*/
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*/
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static TCGv temp_new(DisasContext *ctx)
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{
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assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
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return ctx->temp[ctx->ntemp++] = tcg_temp_new();
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}
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static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
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static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
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{
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{
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TCGv t;
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TCGv t;
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@ -332,11 +323,11 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
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case EXT_NONE:
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case EXT_NONE:
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break;
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break;
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case EXT_SIGN:
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case EXT_SIGN:
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t = temp_new(ctx);
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t = tcg_temp_new();
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tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
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tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
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return t;
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return t;
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case EXT_ZERO:
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case EXT_ZERO:
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t = temp_new(ctx);
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t = tcg_temp_new();
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tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
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tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
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return t;
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return t;
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default:
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default:
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@ -364,7 +355,7 @@ static TCGv get_gprh(DisasContext *ctx, int reg_num)
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static TCGv dest_gpr(DisasContext *ctx, int reg_num)
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static TCGv dest_gpr(DisasContext *ctx, int reg_num)
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{
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{
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if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
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if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
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return temp_new(ctx);
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return tcg_temp_new();
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}
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}
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return cpu_gpr[reg_num];
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return cpu_gpr[reg_num];
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}
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}
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@ -372,7 +363,7 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
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static TCGv dest_gprh(DisasContext *ctx, int reg_num)
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static TCGv dest_gprh(DisasContext *ctx, int reg_num)
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{
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{
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if (reg_num == 0) {
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if (reg_num == 0) {
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return temp_new(ctx);
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return tcg_temp_new();
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}
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}
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return cpu_gprh[reg_num];
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return cpu_gprh[reg_num];
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}
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}
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@ -575,7 +566,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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/* Compute a canonical address from a register plus offset. */
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/* Compute a canonical address from a register plus offset. */
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static TCGv get_address(DisasContext *ctx, int rs1, int imm)
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static TCGv get_address(DisasContext *ctx, int rs1, int imm)
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{
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{
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TCGv addr = temp_new(ctx);
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TCGv addr = tcg_temp_new();
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TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
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TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
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tcg_gen_addi_tl(addr, src1, imm);
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tcg_gen_addi_tl(addr, src1, imm);
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@ -593,7 +584,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
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/* Compute a canonical address from a register plus reg offset. */
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/* Compute a canonical address from a register plus reg offset. */
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static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
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static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
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{
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{
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TCGv addr = temp_new(ctx);
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TCGv addr = tcg_temp_new();
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TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
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TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
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tcg_gen_add_tl(addr, src1, offs);
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tcg_gen_add_tl(addr, src1, offs);
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@ -1197,8 +1188,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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ctx->misa_mxl_max = env->misa_mxl_max;
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ctx->misa_mxl_max = env->misa_mxl_max;
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ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
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ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
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ctx->cs = cs;
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ctx->cs = cs;
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ctx->ntemp = 0;
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memset(ctx->temp, 0, sizeof(ctx->temp));
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ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
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ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
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ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
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ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
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ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
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ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
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@ -1223,18 +1212,11 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPURISCVState *env = cpu->env_ptr;
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CPURISCVState *env = cpu->env_ptr;
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uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
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uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
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int i;
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ctx->ol = ctx->xl;
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ctx->ol = ctx->xl;
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decode_opc(env, ctx, opcode16);
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decode_opc(env, ctx, opcode16);
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ctx->base.pc_next = ctx->pc_succ_insn;
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ctx->base.pc_next = ctx->pc_succ_insn;
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for (i = ctx->ntemp - 1; i >= 0; --i) {
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tcg_temp_free(ctx->temp[i]);
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ctx->temp[i] = NULL;
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}
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ctx->ntemp = 0;
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/* Only the first insn within a TB is allowed to cross a page boundary. */
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/* Only the first insn within a TB is allowed to cross a page boundary. */
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if (ctx->base.is_jmp == DISAS_NEXT) {
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if (ctx->base.is_jmp == DISAS_NEXT) {
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if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
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if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
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