target/ppc: Avoid tcg_const_* in fp-impl.c.inc
All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx)
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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gen_reset_fpstatus();
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crf = tcg_const_i32(crfD(ctx->opcode));
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crf = tcg_constant_i32(crfD(ctx->opcode));
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get_fpr(t0, rA(ctx->opcode));
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get_fpr(t1, rB(ctx->opcode));
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gen_helper_fcmpo(cpu_env, t0, t1, crf);
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@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx)
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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gen_reset_fpstatus();
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crf = tcg_const_i32(crfD(ctx->opcode));
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crf = tcg_constant_i32(crfD(ctx->opcode));
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get_fpr(t0, rA(ctx->opcode));
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get_fpr(t1, rB(ctx->opcode));
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gen_helper_fcmpu(cpu_env, t0, t1, crf);
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@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx)
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tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
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~((0xF << shift) & FP_EX_CLEAR_BITS));
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/* FEX and VX need to be updated, so don't set fpscr directly */
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tmask = tcg_const_i32(1 << nibble);
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tmask = tcg_constant_i32(1 << nibble);
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gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
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}
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@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx)
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crb = 31 - crbD(ctx->opcode);
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gen_reset_fpstatus();
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if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
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TCGv_i32 t0;
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t0 = tcg_const_i32(crb);
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gen_helper_fpscr_clrbit(cpu_env, t0);
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gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
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}
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx)
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crb = 31 - crbD(ctx->opcode);
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/* XXX: we pretend we can only do IEEE floating-point computations */
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if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
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TCGv_i32 t0;
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t0 = tcg_const_i32(crb);
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gen_helper_fpscr_setbit(cpu_env, t0);
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gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
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}
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx)
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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return;
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}
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if (l) {
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t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
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if (!l) {
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t0 = tcg_constant_i32(flm << (w * 8));
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} else if (ctx->insns_flags2 & PPC2_ISA205) {
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t0 = tcg_constant_i32(0xffff);
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} else {
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t0 = tcg_const_i32(flm << (w * 8));
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t0 = tcg_constant_i32(0xff);
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}
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t1 = tcg_temp_new_i64();
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get_fpr(t1, rB(ctx->opcode));
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@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx)
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return;
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}
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sh = (8 * w) + 7 - bf;
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t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
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t1 = tcg_const_i32(1 << sh);
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t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
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t1 = tcg_constant_i32(1 << sh);
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gen_helper_store_fpscr(cpu_env, t0, t1);
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if (unlikely(Rc(ctx->opcode) != 0)) {
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tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
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