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target/tricore: Fix OPC2_32_RCRW_IMASK translation 

we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
This commit is contained in:
Bastian Koppelmann 2023-02-02 13:04:23 +01:00
parent 969d09c3a6
commit 65e57fdb25
1 changed files with 3 additions and 3 deletions
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6
target/tricore/translate.c
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@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx)
switch (op2) {
case OPC2_32_RCRW_IMASK:
tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
tcg_gen_movi_tl(temp2, (1 << width) - 1);
tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
tcg_gen_movi_tl(temp2, const4);
tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
break;
case OPC2_32_RCRW_INSERT:
temp3 = tcg_temp_new();