target/tricore: Fix OPC2_32_RCRW_IMASK translation
we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx)
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switch (op2) {
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case OPC2_32_RCRW_IMASK:
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tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
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tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
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tcg_gen_movi_tl(temp2, (1 << width) - 1);
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tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
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tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp);
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tcg_gen_movi_tl(temp2, const4);
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tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
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tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp);
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break;
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case OPC2_32_RCRW_INSERT:
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temp3 = tcg_temp_new();
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