target/arm: Implement SVE gather loads
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180627043328.11531-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
dec6cf6b43
commit
673e9fa6c2
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@ -959,6 +959,73 @@ DEF_HELPER_FLAGS_4(sve_st1hd_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
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DEF_HELPER_FLAGS_4(sve_st1sd_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbsu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhsu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldssu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbss_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhss_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbsu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhsu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldssu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbss_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhss_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbdu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhdu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldsdu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldddu_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbds_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhds_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldsds_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbdu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhdu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldsdu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldddu_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbds_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhds_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldsds_zss, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbdu_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhdu_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldsdu_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldddu_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldbds_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldhds_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_ldsds_zd, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_stbs_zsu, TCG_CALL_NO_WG,
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void, env, ptr, ptr, ptr, tl, i32)
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DEF_HELPER_FLAGS_6(sve_sths_zsu, TCG_CALL_NO_WG,
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@ -80,6 +80,8 @@
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&rpri_load rd pg rn imm dtype nreg
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&rprr_store rd pg rn rm msz esz nreg
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&rpri_store rd pg rn imm msz esz nreg
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&rprr_gather_load rd pg rn rm esz msz u ff xs scale
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&rpri_gather_load rd pg rn imm esz msz u ff
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&rprr_scatter_store rd pg rn rm esz msz xs scale
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###########################################################################
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@ -194,6 +196,22 @@
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@rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
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&rpri_load dtype=%msz_dtype
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# Gather Loads.
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@rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
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&rprr_gather_load xs=2
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@rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
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&rprr_gather_load
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@rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
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&rprr_gather_load
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@rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
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&rprr_gather_load
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@rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
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&rprr_gather_load xs=2
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@rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
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&rprr_gather_load xs=2
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@rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
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&rpri_gather_load
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# Stores; user must fill in ESZ, MSZ, NREG as needed.
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@rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
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@rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
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@ -759,6 +777,19 @@ LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
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LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
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&rpri_load dtype=%dtype_23_13 nreg=0
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# SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
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# SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
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LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
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@rprr_g_load_xs_u esz=2 msz=0 scale=0
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LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
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@rprr_g_load_xs_u_sc esz=2 msz=1
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LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
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@rprr_g_load_xs_sc esz=2 msz=2 u=1
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# SVE 32-bit gather load (vector plus immediate)
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LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
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@rpri_g_load esz=2
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### SVE Memory Contiguous Load Group
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# SVE contiguous load (scalar plus scalar)
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@ -808,6 +839,32 @@ PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
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### SVE Memory 64-bit Gather Group
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# SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
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# SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
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LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
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@rprr_g_load_xs_u esz=3 msz=0 scale=0
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LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
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@rprr_g_load_xs_u_sc esz=3 msz=1
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LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
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@rprr_g_load_xs_u_sc esz=3 msz=2
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LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
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@rprr_g_load_xs_sc esz=3 msz=3 u=1
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# SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
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# SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
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LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
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@rprr_g_load_u esz=3 msz=0 scale=0
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LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
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@rprr_g_load_u_sc esz=3 msz=1
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LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
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@rprr_g_load_u_sc esz=3 msz=2
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LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
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@rprr_g_load_sc esz=3 msz=3 u=1
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# SVE 64-bit gather load (vector plus immediate)
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LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
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@rpri_g_load esz=3
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# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
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PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
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@ -3714,6 +3714,83 @@ void HELPER(sve_st4dd_r)(CPUARMState *env, void *vg,
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}
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}
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/* Loads with a vector index. */
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#define DO_LD1_ZPZ_S(NAME, TYPEI, TYPEM, FN) \
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void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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intptr_t i, oprsz = simd_oprsz(desc); \
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unsigned scale = simd_data(desc); \
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uintptr_t ra = GETPC(); \
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for (i = 0; i < oprsz; i++) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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TYPEM m = 0; \
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if (pg & 1) { \
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target_ulong off = *(TYPEI *)(vm + H1_4(i)); \
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m = FN(env, base + (off << scale), ra); \
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} \
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*(uint32_t *)(vd + H1_4(i)) = m; \
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i += 4, pg >>= 4; \
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} while (i & 15); \
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} \
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}
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#define DO_LD1_ZPZ_D(NAME, TYPEI, TYPEM, FN) \
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void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm, \
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target_ulong base, uint32_t desc) \
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{ \
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intptr_t i, oprsz = simd_oprsz(desc) / 8; \
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unsigned scale = simd_data(desc); \
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uintptr_t ra = GETPC(); \
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uint64_t *d = vd, *m = vm; uint8_t *pg = vg; \
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for (i = 0; i < oprsz; i++) { \
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TYPEM mm = 0; \
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if (pg[H1(i)] & 1) { \
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target_ulong off = (TYPEI)m[i]; \
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mm = FN(env, base + (off << scale), ra); \
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} \
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d[i] = mm; \
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} \
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}
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DO_LD1_ZPZ_S(sve_ldbsu_zsu, uint32_t, uint8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_S(sve_ldhsu_zsu, uint32_t, uint16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_S(sve_ldssu_zsu, uint32_t, uint32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_S(sve_ldbss_zsu, uint32_t, int8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_S(sve_ldhss_zsu, uint32_t, int16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_S(sve_ldbsu_zss, int32_t, uint8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_S(sve_ldhsu_zss, int32_t, uint16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_S(sve_ldssu_zss, int32_t, uint32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_S(sve_ldbss_zss, int32_t, int8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_S(sve_ldhss_zss, int32_t, int16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldbdu_zsu, uint32_t, uint8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_D(sve_ldhdu_zsu, uint32_t, uint16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldsdu_zsu, uint32_t, uint32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_D(sve_ldddu_zsu, uint32_t, uint64_t, cpu_ldq_data_ra)
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DO_LD1_ZPZ_D(sve_ldbds_zsu, uint32_t, int8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_D(sve_ldhds_zsu, uint32_t, int16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldsds_zsu, uint32_t, int32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_D(sve_ldbdu_zss, int32_t, uint8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_D(sve_ldhdu_zss, int32_t, uint16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldsdu_zss, int32_t, uint32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_D(sve_ldddu_zss, int32_t, uint64_t, cpu_ldq_data_ra)
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DO_LD1_ZPZ_D(sve_ldbds_zss, int32_t, int8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_D(sve_ldhds_zss, int32_t, int16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldsds_zss, int32_t, int32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_D(sve_ldbdu_zd, uint64_t, uint8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_D(sve_ldhdu_zd, uint64_t, uint16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldsdu_zd, uint64_t, uint32_t, cpu_ldl_data_ra)
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DO_LD1_ZPZ_D(sve_ldddu_zd, uint64_t, uint64_t, cpu_ldq_data_ra)
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DO_LD1_ZPZ_D(sve_ldbds_zd, uint64_t, int8_t, cpu_ldub_data_ra)
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DO_LD1_ZPZ_D(sve_ldhds_zd, uint64_t, int16_t, cpu_lduw_data_ra)
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DO_LD1_ZPZ_D(sve_ldsds_zd, uint64_t, int32_t, cpu_ldl_data_ra)
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/* Stores with a vector index. */
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#define DO_ST1_ZPZ_S(NAME, TYPEI, FN) \
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@ -4255,6 +4255,106 @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, int scale,
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tcg_temp_free_i32(desc);
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}
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/* Indexed by [ff][xs][u][msz]. */
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static gen_helper_gvec_mem_scatter * const gather_load_fn32[2][2][2][3] = {
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{ { { gen_helper_sve_ldbss_zsu,
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gen_helper_sve_ldhss_zsu,
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NULL, },
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{ gen_helper_sve_ldbsu_zsu,
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gen_helper_sve_ldhsu_zsu,
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gen_helper_sve_ldssu_zsu, } },
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{ { gen_helper_sve_ldbss_zss,
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gen_helper_sve_ldhss_zss,
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NULL, },
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{ gen_helper_sve_ldbsu_zss,
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gen_helper_sve_ldhsu_zss,
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gen_helper_sve_ldssu_zss, } } },
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/* TODO fill in first-fault handlers */
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};
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/* Note that we overload xs=2 to indicate 64-bit offset. */
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static gen_helper_gvec_mem_scatter * const gather_load_fn64[2][3][2][4] = {
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{ { { gen_helper_sve_ldbds_zsu,
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gen_helper_sve_ldhds_zsu,
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gen_helper_sve_ldsds_zsu,
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NULL, },
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{ gen_helper_sve_ldbdu_zsu,
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gen_helper_sve_ldhdu_zsu,
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gen_helper_sve_ldsdu_zsu,
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gen_helper_sve_ldddu_zsu, } },
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{ { gen_helper_sve_ldbds_zss,
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gen_helper_sve_ldhds_zss,
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gen_helper_sve_ldsds_zss,
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NULL, },
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{ gen_helper_sve_ldbdu_zss,
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gen_helper_sve_ldhdu_zss,
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gen_helper_sve_ldsdu_zss,
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gen_helper_sve_ldddu_zss, } },
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{ { gen_helper_sve_ldbds_zd,
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gen_helper_sve_ldhds_zd,
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gen_helper_sve_ldsds_zd,
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NULL, },
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{ gen_helper_sve_ldbdu_zd,
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gen_helper_sve_ldhdu_zd,
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gen_helper_sve_ldsdu_zd,
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gen_helper_sve_ldddu_zd, } } },
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/* TODO fill in first-fault handlers */
|
||||
};
|
||||
|
||||
static bool trans_LD1_zprz(DisasContext *s, arg_LD1_zprz *a, uint32_t insn)
|
||||
{
|
||||
gen_helper_gvec_mem_scatter *fn = NULL;
|
||||
|
||||
if (!sve_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
switch (a->esz) {
|
||||
case MO_32:
|
||||
fn = gather_load_fn32[a->ff][a->xs][a->u][a->msz];
|
||||
break;
|
||||
case MO_64:
|
||||
fn = gather_load_fn64[a->ff][a->xs][a->u][a->msz];
|
||||
break;
|
||||
}
|
||||
assert(fn != NULL);
|
||||
|
||||
do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz,
|
||||
cpu_reg_sp(s, a->rn), fn);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a, uint32_t insn)
|
||||
{
|
||||
gen_helper_gvec_mem_scatter *fn = NULL;
|
||||
TCGv_i64 imm;
|
||||
|
||||
if (a->esz < a->msz || (a->esz == a->msz && !a->u)) {
|
||||
return false;
|
||||
}
|
||||
if (!sve_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
switch (a->esz) {
|
||||
case MO_32:
|
||||
fn = gather_load_fn32[a->ff][0][a->u][a->msz];
|
||||
break;
|
||||
case MO_64:
|
||||
fn = gather_load_fn64[a->ff][2][a->u][a->msz];
|
||||
break;
|
||||
}
|
||||
assert(fn != NULL);
|
||||
|
||||
/* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x])
|
||||
* by loading the immediate into the scalar parameter.
|
||||
*/
|
||||
imm = tcg_const_i64(a->imm << a->msz);
|
||||
do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, fn);
|
||||
tcg_temp_free_i64(imm);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
|
||||
{
|
||||
/* Indexed by [xs][msz]. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue