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target/riscv: Fix check for vector load/store instructions when EEW=64 

The V extension supports all vector load and store instructions except
the V extension does not support EEW=64 for index values when XLEN=32.
(Section 18.3)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-15 10:05:37 +08:00 committed by Palmer Dabbelt
parent e80865e5f3
commit 6ad831ebf1
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1 changed files with 4 additions and 5 deletions
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9
target/riscv/insn_trans/trans_rvv.c.inc
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@ -287,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
require_nf(vd, nf, s->lmul);
/*
* All Zve* extensions support all vector load and store instructions,
* except Zve64* extensions do not support EEW=64 for index values
* when XLEN=32. (Section 18.2)
* V extension supports all vector load and store instructions,
* except V extension does not support EEW=64 for index values
* when XLEN=32. (Section 18.3)
*/
if (get_xl(s) == MXL_RV32) {
ret &= (!has_ext(s, RVV) &&
s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
ret &= (eew != MO_64);
}
return ret;