target/riscv: Add support for Zvfh/zvfhmin extensions
Zvfh supports vector float point instructions with SEW = 16 and supports conversions between 8-bit integers and binary16 values. Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-12-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -40,6 +40,7 @@ static bool require_rvf(DisasContext *s)
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switch (s->sew) {
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case MO_16:
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return s->cfg_ptr->ext_zvfh;
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case MO_32:
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return s->cfg_ptr->ext_zve32f;
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case MO_64:
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@ -57,6 +58,25 @@ static bool require_scale_rvf(DisasContext *s)
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switch (s->sew) {
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case MO_8:
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return s->cfg_ptr->ext_zvfh;
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case MO_16:
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return s->cfg_ptr->ext_zve32f;
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case MO_32:
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return s->cfg_ptr->ext_zve64d;
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default:
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return false;
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}
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}
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static bool require_scale_rvfmin(DisasContext *s)
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{
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if (s->mstatus_fs == 0) {
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return false;
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}
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switch (s->sew) {
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case MO_8:
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return s->cfg_ptr->ext_zvfhmin;
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case MO_16:
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return s->cfg_ptr->ext_zve32f;
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case MO_32:
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@ -2798,7 +2818,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
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static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
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{
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return opfv_widen_check(s, a) &&
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require_scale_rvf(s) &&
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require_scale_rvfmin(s) &&
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(s->sew != MO_8);
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}
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@ -2909,6 +2929,13 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
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}
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static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
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{
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return opfv_narrow_check(s, a) &&
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require_scale_rvfmin(s) &&
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(s->sew != MO_8);
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}
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static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
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{
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return opfv_narrow_check(s, a) &&
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require_scale_rvf(s) &&
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@ -2952,7 +2979,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w,
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GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
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RISCV_FRM_DYN)
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/* Reuse the helper function from vfncvt.f.f.w */
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GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
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GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
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RISCV_FRM_ROD)
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static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
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