target/riscv: Fix check for vector load/store instructions when EEW=64
The V extension supports all vector load and store instructions except the V extension does not support EEW=64 for index values when XLEN=32. (Section 18.3) Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -287,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
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require_nf(vd, nf, s->lmul);
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require_nf(vd, nf, s->lmul);
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/*
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/*
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* All Zve* extensions support all vector load and store instructions,
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* V extension supports all vector load and store instructions,
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* except Zve64* extensions do not support EEW=64 for index values
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* except V extension does not support EEW=64 for index values
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* when XLEN=32. (Section 18.2)
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* when XLEN=32. (Section 18.3)
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*/
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*/
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if (get_xl(s) == MXL_RV32) {
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if (get_xl(s) == MXL_RV32) {
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ret &= (!has_ext(s, RVV) &&
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ret &= (eew != MO_64);
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s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
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}
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}
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return ret;
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return ret;
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