target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
Since DDI0487F.a, the RW bit is RAO/WI. When specifically targeting such a cpu, e.g. cortex-a76, it is legitimate to ignore the bit within the secure monitor. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -3854,6 +3854,11 @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
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}
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}
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static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
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}
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static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
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{
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{
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
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return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
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@ -1747,6 +1747,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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value |= SCR_FW | SCR_AW; /* RES1 */
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value |= SCR_FW | SCR_AW; /* RES1 */
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valid_mask &= ~SCR_NET; /* RES0 */
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valid_mask &= ~SCR_NET; /* RES0 */
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if (!cpu_isar_feature(aa64_aa32_el1, cpu) &&
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!cpu_isar_feature(aa64_aa32_el2, cpu)) {
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value |= SCR_RW; /* RAO/WI */
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}
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if (cpu_isar_feature(aa64_ras, cpu)) {
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if (cpu_isar_feature(aa64_ras, cpu)) {
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valid_mask |= SCR_TERR;
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valid_mask |= SCR_TERR;
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}
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}
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