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target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP 

Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by
using register addition operations.

This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R
and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands
to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying
`rs' to `rd' verbatim.  This is not the case with OPC_ADDIU where a
sign-extension from bit #31 is made, unless in the uninteresting case of
`rs' being 0, losing the upper 32 bits of the value copied for any
proper 64-bit values.

This also serves as an optimization as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Maciej W. Rozycki 2014-11-12 15:21:53 +00:00 committed by Leon Alrae
parent 81a423e6c6
commit 7215d7e7ae
1 changed files with 3 additions and 3 deletions
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6
target-mips/translate.c
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@ -13936,8 +13936,8 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
rs = rs_rt_enc[enc_rs];
rt = rs_rt_enc[enc_rt];
gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
gen_arith_imm(ctx, OPC_ADDIU, re, rt, 0);
gen_arith(ctx, OPC_ADDU, rd, rs, 0);
gen_arith(ctx, OPC_ADDU, re, rt, 0);
}
break;
case LBU16:
@ -14018,7 +14018,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx)
int rd = uMIPS_RD5(ctx->opcode);
int rs = uMIPS_RS5(ctx->opcode);
gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
gen_arith(ctx, OPC_ADDU, rd, rs, 0);
}
break;
case ANDI16: