target/arm: Move get_phys_addr_pmsav8 to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
1f2e87e5ab
commit
730d5c31d8
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@ -11970,81 +11970,6 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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return !(*prot & (1 << access_type));
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}
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bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, target_ulong *page_size,
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ARMMMUFaultInfo *fi)
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{
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uint32_t secure = regime_is_secure(env, mmu_idx);
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V8M_SAttributes sattrs = {};
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bool ret;
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bool mpu_is_subpage;
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
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if (access_type == MMU_INST_FETCH) {
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/* Instruction fetches always use the MMU bank and the
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* transaction attribute determined by the fetch address,
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* regardless of CPU state. This is painful for QEMU
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* to handle, because it would mean we need to encode
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* into the mmu_idx not just the (user, negpri) information
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* for the current security state but also that for the
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* other security state, which would balloon the number
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* of mmu_idx values needed alarmingly.
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* Fortunately we can avoid this because it's not actually
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* possible to arbitrarily execute code from memory with
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* the wrong security attribute: it will always generate
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* an exception of some kind or another, apart from the
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* special case of an NS CPU executing an SG instruction
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* in S&NSC memory. So we always just fail the translation
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* here and sort things out in the exception handler
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* (including possibly emulating an SG instruction).
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*/
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if (sattrs.ns != !secure) {
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if (sattrs.nsc) {
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fi->type = ARMFault_QEMU_NSCExec;
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} else {
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fi->type = ARMFault_QEMU_SFault;
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}
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*page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
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*phys_ptr = address;
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*prot = 0;
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return true;
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}
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} else {
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/* For data accesses we always use the MMU bank indicated
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* by the current CPU state, but the security attributes
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* might downgrade a secure access to nonsecure.
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*/
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if (sattrs.ns) {
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txattrs->secure = false;
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} else if (!secure) {
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/* NS access to S memory must fault.
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* Architecturally we should first check whether the
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* MPU information for this address indicates that we
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* are doing an unaligned access to Device memory, which
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* should generate a UsageFault instead. QEMU does not
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* currently check for that kind of unaligned access though.
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* If we added it we would need to do so as a special case
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* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
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*/
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fi->type = ARMFault_QEMU_SFault;
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*page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
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*phys_ptr = address;
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*prot = 0;
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return true;
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}
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}
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}
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ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
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txattrs, prot, &mpu_is_subpage, fi, NULL);
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*page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
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return ret;
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}
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/* Combine either inner or outer cacheability attributes for normal
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* memory, according to table D4-42 and pseudocode procedure
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* CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
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@ -605,6 +605,83 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
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return !(*prot & (1 << access_type));
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}
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static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, target_ulong *page_size,
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ARMMMUFaultInfo *fi)
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{
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uint32_t secure = regime_is_secure(env, mmu_idx);
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V8M_SAttributes sattrs = {};
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bool ret;
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bool mpu_is_subpage;
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
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if (access_type == MMU_INST_FETCH) {
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/*
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* Instruction fetches always use the MMU bank and the
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* transaction attribute determined by the fetch address,
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* regardless of CPU state. This is painful for QEMU
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* to handle, because it would mean we need to encode
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* into the mmu_idx not just the (user, negpri) information
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* for the current security state but also that for the
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* other security state, which would balloon the number
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* of mmu_idx values needed alarmingly.
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* Fortunately we can avoid this because it's not actually
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* possible to arbitrarily execute code from memory with
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* the wrong security attribute: it will always generate
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* an exception of some kind or another, apart from the
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* special case of an NS CPU executing an SG instruction
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* in S&NSC memory. So we always just fail the translation
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* here and sort things out in the exception handler
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* (including possibly emulating an SG instruction).
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*/
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if (sattrs.ns != !secure) {
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if (sattrs.nsc) {
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fi->type = ARMFault_QEMU_NSCExec;
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} else {
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fi->type = ARMFault_QEMU_SFault;
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}
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*page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
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*phys_ptr = address;
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*prot = 0;
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return true;
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}
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} else {
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/*
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* For data accesses we always use the MMU bank indicated
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* by the current CPU state, but the security attributes
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* might downgrade a secure access to nonsecure.
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*/
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if (sattrs.ns) {
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txattrs->secure = false;
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} else if (!secure) {
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/*
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* NS access to S memory must fault.
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* Architecturally we should first check whether the
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* MPU information for this address indicates that we
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* are doing an unaligned access to Device memory, which
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* should generate a UsageFault instead. QEMU does not
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* currently check for that kind of unaligned access though.
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* If we added it we would need to do so as a special case
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* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
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*/
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fi->type = ARMFault_QEMU_SFault;
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*page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
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*phys_ptr = address;
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*prot = 0;
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return true;
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}
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}
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}
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ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr,
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txattrs, prot, &mpu_is_subpage, fi, NULL);
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*page_size = sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE;
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return ret;
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}
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/**
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* get_phys_addr - get the physical address for this virtual address
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*
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@ -41,11 +41,6 @@ void get_phys_addr_pmsav7_default(CPUARMState *env,
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int32_t address, int *prot);
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bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user);
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bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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int *prot, target_ulong *page_size,
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ARMMMUFaultInfo *fi);
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bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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bool s1_is_el0,
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