hw/arm/exynos4210: Put external GIC into state struct
Switch the creation of the external GIC to the new-style "embedded in state struct" approach, so we can easily refer to the object elsewhere during realize. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
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@ -648,7 +648,7 @@ M: Peter Maydell <peter.maydell@linaro.org>
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L: qemu-arm@nongnu.org
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L: qemu-arm@nongnu.org
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S: Odd Fixes
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S: Odd Fixes
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F: hw/*/exynos*
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F: hw/*/exynos*
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F: include/hw/arm/exynos4210.h
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F: include/hw/*/exynos*
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Calxeda Highbank
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Calxeda Highbank
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M: Rob Herring <robh@kernel.org>
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M: Rob Herring <robh@kernel.org>
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@ -455,10 +455,9 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
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sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
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sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
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/* External GIC */
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/* External GIC */
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dev = qdev_new("exynos4210.gic");
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qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
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qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
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busdev = SYS_BUS_DEVICE(&s->ext_gic);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_realize(busdev, &error_fatal);
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sysbus_realize_and_unref(busdev, &error_fatal);
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/* Map CPU interface */
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/* Map CPU interface */
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sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
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sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
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/* Map Distributer interface */
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/* Map Distributer interface */
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@ -468,7 +467,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
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qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
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qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
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}
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}
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for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
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for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
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s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
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s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
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}
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}
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/* Internal Interrupt Combiner */
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/* Internal Interrupt Combiner */
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@ -686,6 +685,7 @@ static void exynos4210_init(Object *obj)
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}
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}
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object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
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object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
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object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
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}
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}
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static void exynos4210_class_init(ObjectClass *klass, void *data)
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static void exynos4210_class_init(ObjectClass *klass, void *data)
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@ -27,6 +27,7 @@
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#include "qemu/module.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/exynos4210_gic.h"
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#include "hw/arm/exynos4210.h"
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#include "hw/arm/exynos4210.h"
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#include "qom/object.h"
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#include "qom/object.h"
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@ -44,20 +45,6 @@
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#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
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#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
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#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
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#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
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#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
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OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
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struct Exynos4210GicState {
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SysBusDevice parent_obj;
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MemoryRegion cpu_container;
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MemoryRegion dist_container;
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MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
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MemoryRegion dist_alias[EXYNOS4210_NCPUS];
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uint32_t num_cpu;
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DeviceState *gic;
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};
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static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
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static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
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{
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{
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Exynos4210GicState *s = (Exynos4210GicState *)opaque;
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Exynos4210GicState *s = (Exynos4210GicState *)opaque;
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@ -100,7 +87,7 @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
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* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
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* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
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* doesn't figure this out, otherwise and gives spurious warnings.
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* doesn't figure this out, otherwise and gives spurious warnings.
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*/
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*/
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assert(n <= EXYNOS4210_NCPUS);
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assert(n <= EXYNOS4210_GIC_NCPUS);
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for (i = 0; i < n; i++) {
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for (i = 0; i < n; i++) {
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/* Map CPU interface per SMP Core */
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/* Map CPU interface per SMP Core */
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sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
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sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
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@ -27,6 +27,7 @@
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#include "hw/or-irq.h"
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#include "hw/or-irq.h"
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "hw/cpu/a9mpcore.h"
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#include "hw/cpu/a9mpcore.h"
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#include "hw/intc/exynos4210_gic.h"
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#include "target/arm/cpu-qom.h"
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#include "target/arm/cpu-qom.h"
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#include "qom/object.h"
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#include "qom/object.h"
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@ -103,6 +104,7 @@ struct Exynos4210State {
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qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
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qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
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qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
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qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
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A9MPPrivState a9mpcore;
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A9MPPrivState a9mpcore;
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Exynos4210GicState ext_gic;
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};
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};
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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@ -0,0 +1,43 @@
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/*
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* Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
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*
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* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
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* All rights reserved.
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*
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* Evgeny Voevodin <e.voevodin@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_INTC_EXYNOS4210_GIC_H
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#define HW_INTC_EXYNOS4210_GIC_H
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#include "hw/sysbus.h"
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#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
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OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
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#define EXYNOS4210_GIC_NCPUS 2
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struct Exynos4210GicState {
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SysBusDevice parent_obj;
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MemoryRegion cpu_container;
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MemoryRegion dist_container;
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MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
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MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
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uint32_t num_cpu;
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DeviceState *gic;
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};
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#endif
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