Various fixes for recent regressions and new code.
-----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmYJEQMACgkQZ7MCdqhi HK6l0BAAkVf/BXKJxMu3jLvCpK/fBYGytvfHBR9PdWeBwIirqsk3L8eI/Fb5qkMZ NMrfECyHR9LTcWb6/Pi/PGciNNWeyleN6IuVBeWfraIFyfHcxpwEKH8P+cXr5EWq WDg+1GUt9+FHuAC9UdGZ81UzX7qeI9VfD3wHceqJ/XRU3qjj67DPZjTpsvxuP64+ N7MhdEM69F34uiIAn1aNCceXiS00dvtu6lDl3+18TzT8sNc6S3qdyxVcqfRhTJfY FMZIN3j2hQrVOElEQE9vAOeJyjAQCM+U0y3XZIZHFUw/GTwKV0tm08RFnnxprteG 67vR5uXrDEELnU/1PA1YeyaBMA3Z3Nc36XbGf8zTD6rKkS2z0lWMcs72pPIxbMXj c4FdnHaE+Q5ngy5s1p6bm5xM7WOEhrsJkgIu2N0weRroe0nAxywDWw3uQlMoV8Oc Xet/xM2IKdc0PLzTvFO7xKnW3oqavJ4CX/6XgrGBoMDZKO1JRqaMixGtYKmoH/1h 96+jdRbPTZAY8aoiFWW7t065lvdWt74A6QITcn2Kqm04j3MGJfyWMU6dakBzwuri PhOkf40o8qn8KN0JNfSO+IXhYVRRotLO/s9H7TEyQiXm25qrGMIF9FErnbDseZil rGR4eL0lcwJboYH9RSRWg0NNqpUekvqBzdnS+G0Ad3J+qaMYoik= =7UPB -----END PGP SIGNATURE----- Merge tag 'pull-ppc-for-9.0-3-20240331' of https://gitlab.com/npiggin/qemu into staging Various fixes for recent regressions and new code. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmYJEQMACgkQZ7MCdqhi # HK6l0BAAkVf/BXKJxMu3jLvCpK/fBYGytvfHBR9PdWeBwIirqsk3L8eI/Fb5qkMZ # NMrfECyHR9LTcWb6/Pi/PGciNNWeyleN6IuVBeWfraIFyfHcxpwEKH8P+cXr5EWq # WDg+1GUt9+FHuAC9UdGZ81UzX7qeI9VfD3wHceqJ/XRU3qjj67DPZjTpsvxuP64+ # N7MhdEM69F34uiIAn1aNCceXiS00dvtu6lDl3+18TzT8sNc6S3qdyxVcqfRhTJfY # FMZIN3j2hQrVOElEQE9vAOeJyjAQCM+U0y3XZIZHFUw/GTwKV0tm08RFnnxprteG # 67vR5uXrDEELnU/1PA1YeyaBMA3Z3Nc36XbGf8zTD6rKkS2z0lWMcs72pPIxbMXj # c4FdnHaE+Q5ngy5s1p6bm5xM7WOEhrsJkgIu2N0weRroe0nAxywDWw3uQlMoV8Oc # Xet/xM2IKdc0PLzTvFO7xKnW3oqavJ4CX/6XgrGBoMDZKO1JRqaMixGtYKmoH/1h # 96+jdRbPTZAY8aoiFWW7t065lvdWt74A6QITcn2Kqm04j3MGJfyWMU6dakBzwuri # PhOkf40o8qn8KN0JNfSO+IXhYVRRotLO/s9H7TEyQiXm25qrGMIF9FErnbDseZil # rGR4eL0lcwJboYH9RSRWg0NNqpUekvqBzdnS+G0Ad3J+qaMYoik= # =7UPB # -----END PGP SIGNATURE----- # gpg: Signature made Sun 31 Mar 2024 08:30:11 BST # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE * tag 'pull-ppc-for-9.0-3-20240331' of https://gitlab.com/npiggin/qemu: tests/avocado: ppc_hv_tests.py set alpine time before setup-alpine tests/avocado: Fix ppc_hv_tests.py xorriso dependency guard target/ppc: Do not clear MSR[ME] on MCE interrupts to supervisor target/ppc: Fix GDB register indexing on secondary CPUs target/ppc: Restore [H]DEXCR to 64-bits target/ppc/mmu-radix64: Use correct string format in walk_tree() hw/ppc/spapr: Include missing 'sysemu/tcg.h' header spapr: nested: use bitwise NOT operator for flags check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
7901c12bd7
@ -35,6 +35,7 @@
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#include "sysemu/sysemu.h"
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#include "sysemu/hostmem.h"
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#include "sysemu/numa.h"
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#include "sysemu/tcg.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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@ -1511,7 +1511,7 @@ static target_ulong h_guest_getset_state(PowerPCCPU *cpu,
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if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
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gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE;
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}
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if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
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if (flags & ~H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) {
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return H_PARAMETER; /* flag not supported yet */
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}
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@ -5820,7 +5820,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env)
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{
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spr_register(env, SPR_DEXCR, "DEXCR",
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic32,
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&spr_read_generic, &spr_write_generic,
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0);
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spr_register(env, SPR_UDEXCR, "UDEXCR",
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@ -5831,7 +5831,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env)
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spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
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SPR_NOACCESS, SPR_NOACCESS,
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SPR_NOACCESS, SPR_NOACCESS,
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&spr_read_generic, &spr_write_generic32,
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&spr_read_generic, &spr_write_generic,
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0);
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spr_register(env, SPR_UHDEXCR, "UHDEXCR",
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@ -1345,9 +1345,10 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
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* clear (e.g., see FWNMI in PAPR).
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*/
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new_msr |= (target_ulong)MSR_HVB;
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}
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/* machine check exceptions don't have ME set */
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/* HV machine check exceptions don't have ME set */
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new_msr &= ~((target_ulong)1 << MSR_ME);
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}
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msr |= env->error_code;
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break;
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@ -305,6 +305,25 @@ static void gdb_gen_spr_feature(CPUState *cs)
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unsigned int num_regs = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
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ppc_spr_t *spr = &env->spr_cb[i];
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if (!spr->name) {
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continue;
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}
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/*
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* GDB identifies registers based on the order they are
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* presented in the XML. These ids will not match QEMU's
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* representation (which follows the PowerISA).
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*
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* Store the position of the current register description so
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* we can make the correspondence later.
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*/
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spr->gdb_id = num_regs;
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num_regs++;
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}
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if (pcc->gdb_spr.xml) {
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return;
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}
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@ -321,18 +340,8 @@ static void gdb_gen_spr_feature(CPUState *cs)
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}
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gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
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TARGET_LONG_BITS, num_regs,
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TARGET_LONG_BITS, spr->gdb_id,
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"int", "spr");
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/*
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* GDB identifies registers based on the order they are
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* presented in the XML. These ids will not match QEMU's
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* representation (which follows the PowerISA).
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*
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* Store the position of the current register description so
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* we can make the correspondence later.
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*/
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spr->gdb_id = num_regs;
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num_regs++;
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}
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gdb_feature_builder_end(&builder);
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@ -300,8 +300,8 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr,
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if (nlb & mask) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: misaligned page dir/table base: 0x"TARGET_FMT_lx
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" page dir size: 0x"TARGET_FMT_lx"\n",
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"%s: misaligned page dir/table base: 0x%" PRIx64
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" page dir size: 0x%" PRIx64 "\n",
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__func__, nlb, mask + 1);
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nlb &= ~mask;
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}
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@ -324,8 +324,8 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr,
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if (base_addr & mask) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: misaligned page dir base: 0x"TARGET_FMT_lx
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" page dir size: 0x"TARGET_FMT_lx"\n",
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"%s: misaligned page dir base: 0x%" PRIx64
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" page dir size: 0x%" PRIx64 "\n",
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__func__, base_addr, mask + 1);
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base_addr &= ~mask;
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}
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@ -14,6 +14,7 @@ from avocado_qemu import wait_for_console_pattern, exec_command
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import os
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import time
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import subprocess
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from datetime import datetime
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deps = ["xorriso"] # dependent tools needed in the test setup/box.
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@ -42,10 +43,11 @@ def missing_deps():
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# QEMU packages are downloaded and installed on each test. That's not a
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# large download, but it may be more polite to create qcow2 image with
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# QEMU already installed and use that.
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# XXX: The order of these tests seems to matter, see git blame.
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@skipIf(missing_deps(), 'dependencies (%s) not installed' % ','.join(deps))
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@skipUnless(os.getenv('QEMU_TEST_FLAKY_TESTS'), 'Test sometimes gets stuck due to console handling problem')
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@skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
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@skipUnless(os.getenv('SPEED') == 'slow', 'runtime limited')
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@skipIf(missing_deps(), 'dependencies (%s) not installed' % ','.join(deps))
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class HypervisorTest(QemuSystemTest):
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timeout = 1000
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@ -106,6 +108,8 @@ class HypervisorTest(QemuSystemTest):
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exec_command(self, 'root')
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wait_for_console_pattern(self, 'localhost login:')
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wait_for_console_pattern(self, 'You may change this message by editing /etc/motd.')
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# If the time is wrong, SSL certificates can fail.
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exec_command(self, 'date -s "' + datetime.utcnow().strftime('%Y-%m-%d %H:%M:%S' + '"'))
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exec_command(self, 'setup-alpine -qe')
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wait_for_console_pattern(self, 'Updating repository indexes... done.')
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