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target-mips: Don't overuse CPUState 

Scripted conversion:
  sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc]
  sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber 2012-03-14 01:38:22 +01:00
parent 68cee38a9c
commit 7db13fae2c
5 changed files with 274 additions and 274 deletions
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40
target-mips/cpu.h
View File

@ -495,7 +495,7 @@ void r4k_helper_tlbwr (void);
void r4k_helper_tlbp (void);
void r4k_helper_tlbr (void);
void cpu_unassigned_access(CPUState *env, target_phys_addr_t addr,
void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
int is_write, int is_exec, int unused, int size);
#endif
@ -515,12 +515,12 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2
static inline int cpu_mmu_index (CPUState *env)
static inline int cpu_mmu_index (CPUMIPSState *env)
{
return env->hflags & MIPS_HFLAG_KSU;
}
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp)
{
if (newsp)
env->active_tc.gpr[29] = newsp;
@ -528,7 +528,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->active_tc.gpr[2] = 0;
}
static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
int32_t pending;
int32_t status;
@ -636,28 +636,28 @@ CPUMIPSState *cpu_mips_init(const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
/* mips_timer.c */
uint32_t cpu_mips_get_random (CPUState *env);
uint32_t cpu_mips_get_count (CPUState *env);
void cpu_mips_store_count (CPUState *env, uint32_t value);
void cpu_mips_store_compare (CPUState *env, uint32_t value);
void cpu_mips_start_count(CPUState *env);
void cpu_mips_stop_count(CPUState *env);
uint32_t cpu_mips_get_random (CPUMIPSState *env);
uint32_t cpu_mips_get_count (CPUMIPSState *env);
void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);
/* mips_int.c */
void cpu_mips_soft_irq(CPUState *env, int irq, int level);
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* helper.c */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
void do_interrupt (CPUState *env);
void do_interrupt (CPUMIPSState *env);
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
target_phys_addr_t cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
int rw);
#endif
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->active_tc.PC;
@ -665,12 +665,12 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
}
static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls)
{
env->tls_value = newtls;
}
static inline int mips_vpe_active(CPUState *env)
static inline int mips_vpe_active(CPUMIPSState *env)
{
int active = 1;
@ -701,7 +701,7 @@ static inline int mips_vpe_active(CPUState *env)
return active;
}
static inline int cpu_has_work(CPUState *env)
static inline int cpu_has_work(CPUMIPSState *env)
{
int has_work = 0;
@ -730,7 +730,7 @@ static inline int cpu_has_work(CPUState *env)
#include "exec-all.h"
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
{
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;

24
target-mips/helper.c
View File

@ -36,7 +36,7 @@ enum {
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
@ -45,7 +45,7 @@ int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
}
/* fixed mapping MMU emulation */
int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
@ -63,7 +63,7 @@ int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *pro
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint8_t ASID = env->CP0_EntryHi & 0xFF;
@ -99,7 +99,7 @@ int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
return TLBRET_NOMATCH;
}
static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@ -201,7 +201,7 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
}
#endif
static void raise_mmu_exception(CPUState *env, target_ulong address,
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
int exception = 0, error_code = 0;
@ -254,7 +254,7 @@ static void raise_mmu_exception(CPUState *env, target_ulong address,
}
#if !defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
target_phys_addr_t cpu_get_phys_page_debug(CPUMIPSState *env, target_ulong addr)
{
target_phys_addr_t phys_addr;
int prot;
@ -265,7 +265,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
}
#endif
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int mmu_idx)
{
#if !defined(CONFIG_USER_ONLY)
@ -308,7 +308,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
}
#if !defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
target_phys_addr_t cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
{
target_phys_addr_t physical;
int prot;
@ -367,7 +367,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
};
#if !defined(CONFIG_USER_ONLY)
static target_ulong exception_resume_pc (CPUState *env)
static target_ulong exception_resume_pc (CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@ -383,7 +383,7 @@ static target_ulong exception_resume_pc (CPUState *env)
return bad_pc;
}
static void set_hflags_for_handler (CPUState *env)
static void set_hflags_for_handler (CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
env->hflags &= ~(MIPS_HFLAG_M16);
@ -396,7 +396,7 @@ static void set_hflags_for_handler (CPUState *env)
}
#endif
void do_interrupt (CPUState *env)
void do_interrupt (CPUMIPSState *env)
{
#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
@ -637,7 +637,7 @@ void do_interrupt (CPUState *env)
}
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
{
r4k_tlb_t *tlb;
target_ulong addr;

4
target-mips/machine.c
View File

@ -42,7 +42,7 @@ static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
CPUMIPSState *env = opaque;
int i;
/* Save active TC */
@ -190,7 +190,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUState *env = opaque;
CPUMIPSState *env = opaque;
int i;
if (version_id != 3)

124
target-mips/op_helper.c
View File

@ -29,10 +29,10 @@
#endif /* !defined(CONFIG_USER_ONLY) */
#ifndef CONFIG_USER_ONLY
static inline void cpu_mips_tlb_flush (CPUState *env, int flush_global);
static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
#endif
static inline void compute_hflags(CPUState *env)
static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
@ -750,14 +750,14 @@ void helper_sdm (target_ulong addr, target_ulong reglist, uint32_t mem_idx)
#ifndef CONFIG_USER_ONLY
/* SMP helpers. */
static int mips_vpe_is_wfi(CPUState *c)
static int mips_vpe_is_wfi(CPUMIPSState *c)
{
/* If the VPE is halted but otherwise active, it means it's waiting for
an interrupt. */
return c->halted && mips_vpe_active(c);
}
static inline void mips_vpe_wake(CPUState *c)
static inline void mips_vpe_wake(CPUMIPSState *c)
{
/* Dont set ->halted = 0 directly, let it be done via cpu_has_work
because there might be other conditions that state that c should
@ -765,7 +765,7 @@ static inline void mips_vpe_wake(CPUState *c)
cpu_interrupt(c, CPU_INTERRUPT_WAKE);
}
static inline void mips_vpe_sleep(CPUState *c)
static inline void mips_vpe_sleep(CPUMIPSState *c)
{
/* The VPE was shut off, really go to bed.
Reset any old _WAKE requests. */
@ -773,7 +773,7 @@ static inline void mips_vpe_sleep(CPUState *c)
cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
}
static inline void mips_tc_wake(CPUState *c, int tc)
static inline void mips_tc_wake(CPUMIPSState *c, int tc)
{
/* FIXME: TC reschedule. */
if (mips_vpe_active(c) && !mips_vpe_is_wfi(c)) {
@ -781,7 +781,7 @@ static inline void mips_tc_wake(CPUState *c, int tc)
}
}
static inline void mips_tc_sleep(CPUState *c, int tc)
static inline void mips_tc_sleep(CPUMIPSState *c, int tc)
{
/* FIXME: TC reschedule. */
if (!mips_vpe_active(c)) {
@ -791,14 +791,14 @@ static inline void mips_tc_sleep(CPUState *c, int tc)
/* tc should point to an int with the value of the global TC index.
This function will transform it into a local index within the
returned CPUState.
returned CPUMIPSState.
FIXME: This code assumes that all VPEs have the same number of TCs,
which depends on runtime setup. Can probably be fixed by
walking the list of CPUStates. */
static CPUState *mips_cpu_map_tc(int *tc)
walking the list of CPUMIPSStates. */
static CPUMIPSState *mips_cpu_map_tc(int *tc)
{
CPUState *other;
CPUMIPSState *other;
int vpe_idx, nr_threads = env->nr_threads;
int tc_idx = *tc;
@ -823,7 +823,7 @@ static CPUState *mips_cpu_map_tc(int *tc)
These helper call synchronizes the regs for a given cpu. */
/* Called for updates to CP0_Status. */
static void sync_c0_status(CPUState *cpu, int tc)
static void sync_c0_status(CPUMIPSState *cpu, int tc)
{
int32_t tcstatus, *tcst;
uint32_t v = cpu->CP0_Status;
@ -858,7 +858,7 @@ static void sync_c0_status(CPUState *cpu, int tc)
}
/* Called for updates to CP0_TCStatus. */
static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, target_ulong v)
{
uint32_t status;
uint32_t tcu, tmx, tasid, tksu;
@ -889,7 +889,7 @@ static void sync_c0_tcstatus(CPUState *cpu, int tc, target_ulong v)
}
/* Called for updates to CP0_EntryHi. */
static void sync_c0_entryhi(CPUState *cpu, int tc)
static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
{
int32_t *tcst;
uint32_t asid, v = cpu->CP0_EntryHi;
@ -935,7 +935,7 @@ target_ulong helper_mfc0_tcstatus (void)
target_ulong helper_mftc0_tcstatus(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCStatus;
@ -951,7 +951,7 @@ target_ulong helper_mfc0_tcbind (void)
target_ulong helper_mftc0_tcbind(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCBind;
@ -967,7 +967,7 @@ target_ulong helper_mfc0_tcrestart (void)
target_ulong helper_mftc0_tcrestart(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.PC;
@ -983,7 +983,7 @@ target_ulong helper_mfc0_tchalt (void)
target_ulong helper_mftc0_tchalt(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCHalt;
@ -999,7 +999,7 @@ target_ulong helper_mfc0_tccontext (void)
target_ulong helper_mftc0_tccontext(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCContext;
@ -1015,7 +1015,7 @@ target_ulong helper_mfc0_tcschedule (void)
target_ulong helper_mftc0_tcschedule(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCSchedule;
@ -1031,7 +1031,7 @@ target_ulong helper_mfc0_tcschefback (void)
target_ulong helper_mftc0_tcschefback(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.CP0_TCScheFBack;
@ -1047,7 +1047,7 @@ target_ulong helper_mfc0_count (void)
target_ulong helper_mftc0_entryhi(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_EntryHi;
}
@ -1056,7 +1056,7 @@ target_ulong helper_mftc0_cause(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
int32_t tccause;
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc) {
tccause = other->CP0_Cause;
@ -1070,7 +1070,7 @@ target_ulong helper_mftc0_cause(void)
target_ulong helper_mftc0_status(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_Status;
}
@ -1103,7 +1103,7 @@ target_ulong helper_mftc0_debug(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
int32_t tcstatus;
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
tcstatus = other->active_tc.CP0_Debug_tcstatus;
@ -1201,7 +1201,7 @@ void helper_mtc0_vpecontrol (target_ulong arg1)
void helper_mttc0_vpecontrol(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
uint32_t mask;
uint32_t newval;
@ -1217,7 +1217,7 @@ void helper_mttc0_vpecontrol(target_ulong arg1)
target_ulong helper_mftc0_vpecontrol(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
/* FIXME: Mask away return zero on read bits. */
return other->CP0_VPEControl;
}
@ -1225,7 +1225,7 @@ target_ulong helper_mftc0_vpecontrol(void)
target_ulong helper_mftc0_vpeconf0(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_VPEConf0;
}
@ -1250,7 +1250,7 @@ void helper_mtc0_vpeconf0 (target_ulong arg1)
void helper_mttc0_vpeconf0(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
uint32_t mask = 0;
uint32_t newval;
@ -1311,7 +1311,7 @@ void helper_mtc0_tcstatus (target_ulong arg1)
void helper_mttc0_tcstatus (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCStatus = arg1;
@ -1336,7 +1336,7 @@ void helper_mttc0_tcbind (target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
mask |= (1 << CP0TCBd_CurVPE);
@ -1360,7 +1360,7 @@ void helper_mtc0_tcrestart (target_ulong arg1)
void helper_mttc0_tcrestart (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc) {
other->active_tc.PC = arg1;
@ -1390,7 +1390,7 @@ void helper_mtc0_tchalt (target_ulong arg1)
void helper_mttc0_tchalt (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
// TODO: Halt TC / Restart (if allocated+active) TC.
@ -1414,7 +1414,7 @@ void helper_mtc0_tccontext (target_ulong arg1)
void helper_mttc0_tccontext (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCContext = arg1;
@ -1430,7 +1430,7 @@ void helper_mtc0_tcschedule (target_ulong arg1)
void helper_mttc0_tcschedule (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCSchedule = arg1;
@ -1446,7 +1446,7 @@ void helper_mtc0_tcschefback (target_ulong arg1)
void helper_mttc0_tcschefback (target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.CP0_TCScheFBack = arg1;
@ -1542,7 +1542,7 @@ void helper_mtc0_entryhi (target_ulong arg1)
void helper_mttc0_entryhi(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
other->CP0_EntryHi = arg1;
sync_c0_entryhi(other, other_tc);
@ -1584,7 +1584,7 @@ void helper_mtc0_status (target_ulong arg1)
void helper_mttc0_status(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
other->CP0_Status = arg1 & ~0xf1000018;
sync_c0_status(other, other_tc);
@ -1602,7 +1602,7 @@ void helper_mtc0_srsctl (target_ulong arg1)
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
}
static void mtc0_cause(CPUState *cpu, target_ulong arg1)
static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
{
uint32_t mask = 0x00C00300;
uint32_t old = cpu->CP0_Cause;
@ -1638,7 +1638,7 @@ void helper_mtc0_cause(target_ulong arg1)
void helper_mttc0_cause(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
mtc0_cause(other, arg1);
}
@ -1646,7 +1646,7 @@ void helper_mttc0_cause(target_ulong arg1)
target_ulong helper_mftc0_epc(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_EPC;
}
@ -1654,7 +1654,7 @@ target_ulong helper_mftc0_epc(void)
target_ulong helper_mftc0_ebase(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
return other->CP0_EBase;
}
@ -1668,14 +1668,14 @@ void helper_mtc0_ebase (target_ulong arg1)
void helper_mttc0_ebase(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
}
target_ulong helper_mftc0_configx(target_ulong idx)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
switch (idx) {
case 0: return other->CP0_Config0;
@ -1746,7 +1746,7 @@ void helper_mttc0_debug(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
/* XXX: Might be wrong, check with EJTAG spec. */
if (other_tc == other->current_tc)
@ -1787,7 +1787,7 @@ void helper_mtc0_datahi (target_ulong arg1)
target_ulong helper_mftgpr(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.gpr[sel];
@ -1798,7 +1798,7 @@ target_ulong helper_mftgpr(uint32_t sel)
target_ulong helper_mftlo(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.LO[sel];
@ -1809,7 +1809,7 @@ target_ulong helper_mftlo(uint32_t sel)
target_ulong helper_mfthi(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.HI[sel];
@ -1820,7 +1820,7 @@ target_ulong helper_mfthi(uint32_t sel)
target_ulong helper_mftacx(uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.ACX[sel];
@ -1831,7 +1831,7 @@ target_ulong helper_mftacx(uint32_t sel)
target_ulong helper_mftdsp(void)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
return other->active_tc.DSPControl;
@ -1842,7 +1842,7 @@ target_ulong helper_mftdsp(void)
void helper_mttgpr(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.gpr[sel] = arg1;
@ -1853,7 +1853,7 @@ void helper_mttgpr(target_ulong arg1, uint32_t sel)
void helper_mttlo(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.LO[sel] = arg1;
@ -1864,7 +1864,7 @@ void helper_mttlo(target_ulong arg1, uint32_t sel)
void helper_mtthi(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.HI[sel] = arg1;
@ -1875,7 +1875,7 @@ void helper_mtthi(target_ulong arg1, uint32_t sel)
void helper_mttacx(target_ulong arg1, uint32_t sel)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.ACX[sel] = arg1;
@ -1886,7 +1886,7 @@ void helper_mttacx(target_ulong arg1, uint32_t sel)
void helper_mttdsp(target_ulong arg1)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUState *other = mips_cpu_map_tc(&other_tc);
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
if (other_tc == other->current_tc)
other->active_tc.DSPControl = arg1;
@ -1909,7 +1909,7 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(void)
{
CPUState *other_cpu = first_cpu;
CPUMIPSState *other_cpu = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
do {
@ -1925,7 +1925,7 @@ target_ulong helper_dvpe(void)
target_ulong helper_evpe(void)
{
CPUState *other_cpu = first_cpu;
CPUMIPSState *other_cpu = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
do {
@ -1981,14 +1981,14 @@ target_ulong helper_yield(target_ulong arg)
#ifndef CONFIG_USER_ONLY
/* TLB management */
static void cpu_mips_tlb_flush (CPUState *env, int flush_global)
static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
{
/* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush (env, flush_global);
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
while (env->tlb->tlb_in_use > first) {
@ -2316,11 +2316,11 @@ static void do_unaligned_access (target_ulong addr, int is_write, int is_user, v
helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
}
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
void tlb_fill(CPUMIPSState *env1, target_ulong addr, int is_write, int mmu_idx,
void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
CPUMIPSState *saved_env;
unsigned long pc;
int ret;
@ -2343,7 +2343,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
env = saved_env;
}
void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
void cpu_unassigned_access(CPUMIPSState *env1, target_phys_addr_t addr,
int is_write, int is_exec, int unused, int size)
{
env = env1;

356
target-mips/translate.c
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