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target/riscv: Support the v0.6 Hypervisor extension CRSs

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com
Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis 2020-08-12 12:13:44 -07:00
parent 30f663b16f
commit 83028098f4
2 changed files with 43 additions and 0 deletions
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3
target/riscv/cpu_bits.h
View File

@ -197,9 +197,12 @@
#define CSR_HIDELEG 0x603 #define CSR_HIDELEG 0x603
#define CSR_HIE 0x604 #define CSR_HIE 0x604
#define CSR_HCOUNTEREN 0x606 #define CSR_HCOUNTEREN 0x606
#define CSR_HGEIE 0x607
#define CSR_HTVAL 0x643 #define CSR_HTVAL 0x643
#define CSR_HVIP 0x645
#define CSR_HIP 0x644 #define CSR_HIP 0x644
#define CSR_HTINST 0x64A #define CSR_HTINST 0x64A
#define CSR_HGEIP 0xE12
#define CSR_HGATP 0x680 #define CSR_HGATP 0x680
#define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615 #define CSR_HTIMEDELTAH 0x615

40
target/riscv/csr.c
View File

@ -883,12 +883,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
return 0; return 0;
} }
static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
*ret_value &= hip_writable_mask;
return ret;
}
static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value, static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask) target_ulong new_value, target_ulong write_mask)
{ {
int ret = rmw_mip(env, 0, ret_value, new_value, int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask); write_mask & hip_writable_mask);
*ret_value &= hip_writable_mask;
return ret; return ret;
} }
@ -916,6 +929,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
return 0; return 0;
} }
static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
{
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
return 0;
}
static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
{
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
return 0;
}
static int read_htval(CPURISCVState *env, int csrno, target_ulong *val) static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
{ {
*val = env->htval; *val = env->htval;
@ -939,6 +964,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
return 0; return 0;
} }
static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
{
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
return 0;
}
static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
{
qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
return 0;
}
static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val) static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
{ {
*val = env->hgatp; *val = env->hgatp;
@ -1341,11 +1378,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus }, [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg }, [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg }, [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
[CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
[CSR_HIP] = { hmode, NULL, NULL, rmw_hip }, [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { hmode, read_hie, write_hie }, [CSR_HIE] = { hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren }, [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
[CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { hmode, read_htval, write_htval }, [CSR_HTVAL] = { hmode, read_htval, write_htval },
[CSR_HTINST] = { hmode, read_htinst, write_htinst }, [CSR_HTINST] = { hmode, read_htinst, write_htinst },
[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp }, [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta }, [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
#if defined(TARGET_RISCV32) #if defined(TARGET_RISCV32)