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xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers

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Connect CAN0 and CAN1 on the ZynqMP.

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Vikram Garhwal 2020-11-18 11:48:44 -08:00 committed by Peter Maydell
parent 98e5d7a2b7
commit 840c22cd54
3 changed files with 62 additions and 0 deletions
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20
hw/arm/xlnx-zcu102.c
View File

@ -25,6 +25,7 @@
#include "sysemu/qtest.h"
#include "sysemu/device_tree.h"
#include "qom/object.h"
#include "net/can_emu.h"
struct XlnxZCU102 {
MachineState parent_obj;
@ -34,6 +35,8 @@ struct XlnxZCU102 {
bool secure;
bool virt;
CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
struct arm_boot_info binfo;
};
@ -125,6 +128,14 @@ static void xlnx_zcu102_init(MachineState *machine)
object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
&error_fatal);
for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
gchar *bus_name = g_strdup_printf("canbus%d", i);
object_property_set_link(OBJECT(&s->soc), bus_name,
OBJECT(s->canbus[i]), &error_fatal);
g_free(bus_name);
}
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* Create and plug in the SD cards */
@ -208,6 +219,15 @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
s->secure = false;
/* Default to virt (EL2) being disabled */
s->virt = false;
object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
(Object **)&s->canbus[0],
object_property_allow_set_link,
0);
object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
(Object **)&s->canbus[1],
object_property_allow_set_link,
0);
}
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)

34
hw/arm/xlnx-zynqmp.c
View File

@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
21, 22,
};
static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
0xFF060000, 0xFF070000,
};
static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
23, 24,
};
static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
0xFF160000, 0xFF170000,
};
@ -243,6 +251,11 @@ static void xlnx_zynqmp_init(Object *obj)
TYPE_CADENCE_UART);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
object_initialize_child(obj, "can[*]", &s->can[i],
TYPE_XLNX_ZYNQMP_CAN);
}
object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
@ -482,6 +495,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
gic_spi[uart_intr[i]]);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
object_property_set_link(OBJECT(&s->can[i]), "canbus",
OBJECT(s->canbus[i]), &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
gic_spi[can_intr[i]]);
}
object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
@ -619,6 +649,10 @@ static Property xlnx_zynqmp_props[] = {
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
CanBusState *),
DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
CanBusState *),
DEFINE_PROP_END_OF_LIST()
};

8
include/hw/arm/xlnx-zynqmp.h
View File

@ -22,6 +22,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
#include "hw/net/xlnx-zynqmp-can.h"
#include "hw/ide/ahci.h"
#include "hw/sd/sdhci.h"
#include "hw/ssi/xilinx_spips.h"
@ -33,6 +34,7 @@
#include "hw/cpu/cluster.h"
#include "target/arm/cpu.h"
#include "qom/object.h"
#include "net/can_emu.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@ -41,6 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
#define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_NUM_UARTS 2
#define XLNX_ZYNQMP_NUM_CAN 2
#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
#define XLNX_ZYNQMP_NUM_SDHCI 2
#define XLNX_ZYNQMP_NUM_SPIS 2
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
@ -92,6 +96,7 @@ struct XlnxZynqMPState {
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
SysbusAHCIState sata;
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
@ -112,6 +117,9 @@ struct XlnxZynqMPState {
bool virt;
/* Has the RPU subsystem? */
bool has_rpu;
/* CAN bus. */
CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
};
#endif