xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
Connect CAN0 and CAN1 on the ZynqMP. Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com> Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -25,6 +25,7 @@
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#include "sysemu/qtest.h"
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#include "sysemu/device_tree.h"
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#include "qom/object.h"
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#include "net/can_emu.h"
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struct XlnxZCU102 {
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MachineState parent_obj;
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@ -34,6 +35,8 @@ struct XlnxZCU102 {
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bool secure;
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bool virt;
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CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
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struct arm_boot_info binfo;
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};
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@ -125,6 +128,14 @@ static void xlnx_zcu102_init(MachineState *machine)
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object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
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&error_fatal);
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for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
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gchar *bus_name = g_strdup_printf("canbus%d", i);
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object_property_set_link(OBJECT(&s->soc), bus_name,
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OBJECT(s->canbus[i]), &error_fatal);
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g_free(bus_name);
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}
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qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
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/* Create and plug in the SD cards */
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@ -208,6 +219,15 @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
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s->secure = false;
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/* Default to virt (EL2) being disabled */
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s->virt = false;
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object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
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(Object **)&s->canbus[0],
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object_property_allow_set_link,
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0);
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object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
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(Object **)&s->canbus[1],
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object_property_allow_set_link,
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0);
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}
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static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
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@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
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21, 22,
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};
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static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
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0xFF060000, 0xFF070000,
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};
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static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
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23, 24,
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};
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static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
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0xFF160000, 0xFF170000,
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};
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@ -243,6 +251,11 @@ static void xlnx_zynqmp_init(Object *obj)
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TYPE_CADENCE_UART);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
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object_initialize_child(obj, "can[*]", &s->can[i],
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TYPE_XLNX_ZYNQMP_CAN);
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}
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object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
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for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
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@ -482,6 +495,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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gic_spi[uart_intr[i]]);
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}
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for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
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object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
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XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
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object_property_set_link(OBJECT(&s->can[i]), "canbus",
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OBJECT(s->canbus[i]), &error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
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gic_spi[can_intr[i]]);
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}
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object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
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@ -619,6 +649,10 @@ static Property xlnx_zynqmp_props[] = {
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DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
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DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
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CanBusState *),
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DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
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CanBusState *),
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DEFINE_PROP_END_OF_LIST()
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};
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@ -22,6 +22,7 @@
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#include "hw/intc/arm_gic.h"
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#include "hw/net/cadence_gem.h"
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#include "hw/char/cadence_uart.h"
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#include "hw/net/xlnx-zynqmp-can.h"
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#include "hw/ide/ahci.h"
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#include "hw/sd/sdhci.h"
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#include "hw/ssi/xilinx_spips.h"
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@ -33,6 +34,7 @@
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#include "hw/cpu/cluster.h"
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#include "net/can_emu.h"
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#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
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@ -41,6 +43,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
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#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
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#define XLNX_ZYNQMP_NUM_GEMS 4
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#define XLNX_ZYNQMP_NUM_UARTS 2
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#define XLNX_ZYNQMP_NUM_CAN 2
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#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
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#define XLNX_ZYNQMP_NUM_SDHCI 2
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#define XLNX_ZYNQMP_NUM_SPIS 2
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#define XLNX_ZYNQMP_NUM_GDMA_CH 8
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@ -92,6 +96,7 @@ struct XlnxZynqMPState {
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CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
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CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
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XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
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SysbusAHCIState sata;
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SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
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XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
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@ -112,6 +117,9 @@ struct XlnxZynqMPState {
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bool virt;
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/* Has the RPU subsystem? */
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bool has_rpu;
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/* CAN bus. */
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CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
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};
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#endif
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