target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Implement the 2-reg-misc CNT, NOT and RBIT instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -320,6 +320,7 @@ DEF_HELPER_1(neon_cls_s8, i32, i32)
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DEF_HELPER_1(neon_cls_s16, i32, i32)
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DEF_HELPER_1(neon_cls_s32, i32, i32)
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DEF_HELPER_1(neon_cnt_u8, i32, i32)
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DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32)
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DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32)
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@ -1133,6 +1133,18 @@ uint32_t HELPER(neon_cnt_u8)(uint32_t x)
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return x;
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}
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/* Reverse bits in each 8 bit word */
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uint32_t HELPER(neon_rbit_u8)(uint32_t x)
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{
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x = ((x & 0xf0f0f0f0) >> 4)
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| ((x & 0x0f0f0f0f) << 4);
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x = ((x & 0x88888888) >> 3)
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| ((x & 0x44444444) >> 1)
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| ((x & 0x22222222) << 1)
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| ((x & 0x11111111) << 3);
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return x;
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}
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#define NEON_QDMULH16(dest, src1, src2, round) do { \
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uint32_t tmp = (int32_t)(int16_t) src1 * (int16_t) src2; \
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if ((tmp ^ (tmp << 1)) & SIGNBIT) { \
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@ -6222,6 +6222,12 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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TCGCond cond;
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switch (opcode) {
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case 0x5: /* NOT */
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/* This opcode is shared with CNT and RBIT but we have earlier
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* enforced that size == 3 if and only if this is the NOT insn.
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*/
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tcg_gen_not_i64(tcg_rd, tcg_rn);
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break;
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case 0xa: /* CMLT */
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/* 64 bit integer comparison against zero, result is
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* test ? (2^64 - 1) : 0. We implement via setcond(!test) and
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@ -7385,13 +7391,19 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x1: /* REV16 */
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unsupported_encoding(s, insn);
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return;
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case 0x5: /* CNT, NOT, RBIT */
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if ((u == 0 && size > 0) ||
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(u == 1 && size > 1)) {
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unallocated_encoding(s);
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return;
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case 0x5: /* CNT, NOT, RBIT */
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if (u && size == 0) {
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/* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
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size = 3;
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break;
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} else if (u && size == 1) {
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/* RBIT */
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break;
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} else if (!u && size == 0) {
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/* CNT */
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break;
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}
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unsupported_encoding(s, insn);
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unallocated_encoding(s);
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return;
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case 0x2: /* SADDLP, UADDLP */
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case 0x4: /* CLS, CLZ */
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@ -7553,6 +7565,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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} else {
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/* Use helpers for 8 and 16 bit elements */
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switch (opcode) {
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case 0x5: /* CNT, RBIT */
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/* For these two insns size is part of the opcode specifier
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* (handled earlier); they always operate on byte elements.
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*/
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if (u) {
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gen_helper_neon_rbit_u8(tcg_res, tcg_op);
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} else {
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gen_helper_neon_cnt_u8(tcg_res, tcg_op);
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}
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break;
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case 0x8: /* CMGT, CMGE */
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case 0x9: /* CMEQ, CMLE */
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case 0xa: /* CMLT */
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