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target/loongarch: Add fixed point extra instruction translation 

This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-10-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Song Gao 2022-06-06 20:42:59 +08:00 committed by Richard Henderson
parent 94b02d57b0
commit 8708a04a61
5 changed files with 118 additions and 0 deletions
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4
target/loongarch/helper.h
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@ -11,3 +11,7 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_3(asrtle_d, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(asrtgt_d, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_2(cpucfg, TCG_CALL_NO_RWG_SE, tl, env, tl)

68
target/loongarch/insn_trans/trans_extra.c.inc Normal file
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@ -0,0 +1,68 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
static bool trans_break(DisasContext *ctx, arg_break *a)
{
generate_exception(ctx, EXCCODE_BRK);
return true;
}
static bool trans_syscall(DisasContext *ctx, arg_syscall *a)
{
generate_exception(ctx, EXCCODE_SYS);
return true;
}
static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtle_d(cpu_env, src1, src2);
return true;
}
static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
{
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtgt_d(cpu_env, src1, src2);
return true;
}
static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
gen_helper_cpucfg(dest, cpu_env, src1);
gen_set_gpr(a->rd, dest, EXT_NONE);
return true;
}
static bool gen_crc(DisasContext *ctx, arg_rrr *a,
void (*func)(TCGv, TCGv, TCGv, TCGv),
TCGv tsz)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_SIGN);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
func(dest, src2, src1, tsz);
gen_set_gpr(a->rd, dest, EXT_SIGN);
return true;
}
TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))

19
target/loongarch/insns.decode
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@ -17,6 +17,7 @@
&i imm
&r_i rd imm
&rr rd rj
&rr_jk rj rk
&rrr rd rj rk
&rr_i rd rj imm
&hint_r_i hint rj imm
@ -28,6 +29,7 @@
#
@i15 .... ........ ..... imm:15 &i
@rr .... ........ ..... ..... rj:5 rd:5 &rr
@rr_jk .... ........ ..... rk:5 rj:5 ..... &rr_jk
@rrr .... ........ ..... rk:5 rj:5 rd:5 &rrr
@r_i20 .... ... imm:s20 rd:5 &r_i
@rr_ui5 .... ........ ..... imm:5 rj:5 rd:5 &rr_i
@ -237,3 +239,20 @@ ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr
ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr
ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr
ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr
#
# Fixed point extra instruction
#
crc_w_b_w 0000 00000010 01000 ..... ..... ..... @rrr
crc_w_h_w 0000 00000010 01001 ..... ..... ..... @rrr
crc_w_w_w 0000 00000010 01010 ..... ..... ..... @rrr
crc_w_d_w 0000 00000010 01011 ..... ..... ..... @rrr
crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @rrr
crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @rrr
crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @rrr
crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @rrr
break 0000 00000010 10100 ............... @i15
syscall 0000 00000010 10110 ............... @i15
asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk
asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk
cpucfg 0000 00000000 00000 11011 ..... ..... @rr

26
target/loongarch/op_helper.c
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@ -13,6 +13,8 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "internals.h"
#include "qemu/crc32c.h"
#include <zlib.h>
/* Exceptions helpers */
void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
@ -55,3 +57,27 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
do_raise_exception(env, EXCCODE_ADEM, GETPC());
}
}
target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
{
uint8_t buf[8];
target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
m &= mask;
stq_le_p(buf, m);
return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
}
target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
{
uint8_t buf[8];
target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
m &= mask;
stq_le_p(buf, m);
return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
}
target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
{
return rj > 21 ? 0 : env->cpucfg[rj];
}

1
target/loongarch/translate.c
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@ -155,6 +155,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_bit.c.inc"
#include "insn_trans/trans_memory.c.inc"
#include "insn_trans/trans_atomic.c.inc"
#include "insn_trans/trans_extra.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{