Merge patch series "target/riscv: Add support for Svadu extension"
Weiwei Li <liweiwei@iscas.ac.cn> says: This patchset adds support svadu extension. It also fixes some relationship between *envcfg fields and Svpbmt/Sstc extensions. Specification for Svadu extension can be found in: https://github.com/riscv/riscv-svadu * b4-shazam-merge: target/riscv: Export Svadu property target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add csr support for svadu target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Message-ID: <20230224040852.37109-1-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
commit
8e5aded3de
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@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia),
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ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf),
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ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc),
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ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu),
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ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
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ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
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ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
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@ -617,6 +618,11 @@ static void riscv_cpu_reset_hold(Object *obj)
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env->bins = 0;
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env->two_stage_lookup = false;
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env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
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env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
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(cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
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/* Initialized default priorities of local interrupts. */
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for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
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iprio = riscv_cpu_default_priority(i);
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@ -1129,6 +1135,8 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
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DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
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DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
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DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
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DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
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DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
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@ -438,6 +438,7 @@ struct RISCVCPUConfig {
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bool ext_zihintpause;
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bool ext_smstateen;
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bool ext_sstc;
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bool ext_svadu;
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bool ext_svinval;
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bool ext_svnapot;
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bool ext_svpbmt;
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@ -747,10 +747,12 @@ typedef enum RISCVException {
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#define MENVCFG_CBIE (3UL << 4)
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#define MENVCFG_CBCFE BIT(6)
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#define MENVCFG_CBZE BIT(7)
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#define MENVCFG_HADE (1ULL << 61)
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#define MENVCFG_PBMTE (1ULL << 62)
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#define MENVCFG_STCE (1ULL << 63)
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/* For RV32 */
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#define MENVCFGH_HADE BIT(29)
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#define MENVCFGH_PBMTE BIT(30)
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#define MENVCFGH_STCE BIT(31)
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@ -763,10 +765,12 @@ typedef enum RISCVException {
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#define HENVCFG_CBIE MENVCFG_CBIE
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#define HENVCFG_CBCFE MENVCFG_CBCFE
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#define HENVCFG_CBZE MENVCFG_CBZE
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#define HENVCFG_HADE MENVCFG_HADE
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#define HENVCFG_PBMTE MENVCFG_PBMTE
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#define HENVCFG_STCE MENVCFG_STCE
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/* For RV32 */
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#define HENVCFGH_HADE MENVCFGH_HADE
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#define HENVCFGH_PBMTE MENVCFGH_PBMTE
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#define HENVCFGH_STCE MENVCFGH_STCE
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@ -936,9 +936,17 @@ restart:
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return TRANSLATE_FAIL;
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}
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bool pbmte = env->menvcfg & MENVCFG_PBMTE;
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bool hade = env->menvcfg & MENVCFG_HADE;
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if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
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pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
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hade = hade && (env->henvcfg & HENVCFG_HADE);
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}
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if (riscv_cpu_sxl(env) == MXL_RV32) {
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ppn = pte >> PTE_PPN_SHIFT;
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} else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) {
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} else if (pbmte || cpu->cfg.ext_svnapot) {
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ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
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} else {
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ppn = pte >> PTE_PPN_SHIFT;
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@ -950,7 +958,7 @@ restart:
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if (!(pte & PTE_V)) {
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/* Invalid PTE */
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return TRANSLATE_FAIL;
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} else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) {
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} else if (!pbmte && (pte & PTE_PBMT)) {
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return TRANSLATE_FAIL;
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} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
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/* Inner PTE, continue walking */
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@ -992,6 +1000,10 @@ restart:
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/* Page table updates need to be atomic with MTTCG enabled */
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if (updated_pte != pte) {
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if (!hade) {
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return TRANSLATE_FAIL;
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}
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/*
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* - if accessed or dirty bits need updating, and the PTE is
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* in RAM, then we do so atomically with a compare and swap.
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@ -1879,10 +1879,13 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
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static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
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uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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mask |= MENVCFG_PBMTE | MENVCFG_STCE;
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mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cfg->ext_sstc ? MENVCFG_STCE : 0) |
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(cfg->ext_svadu ? MENVCFG_HADE : 0);
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}
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env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
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@ -1899,7 +1902,10 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
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static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
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RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
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uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cfg->ext_sstc ? MENVCFG_STCE : 0) |
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(cfg->ext_svadu ? MENVCFG_HADE : 0);
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uint64_t valh = (uint64_t)val << 32;
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env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
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@ -1979,7 +1985,13 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
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return ret;
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}
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*val = env->henvcfg;
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/*
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* henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
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* henvcfg.stce is read_only 0 when menvcfg.stce = 0
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* henvcfg.hade is read_only 0 when menvcfg.hade = 0
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*/
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*val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
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env->menvcfg);
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return RISCV_EXCP_NONE;
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}
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@ -1995,7 +2007,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
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}
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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mask |= HENVCFG_PBMTE | HENVCFG_STCE;
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mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE);
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}
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env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
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@ -2013,14 +2025,16 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
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return ret;
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}
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*val = env->henvcfg >> 32;
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*val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) |
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env->menvcfg)) >> 32;
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return RISCV_EXCP_NONE;
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}
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static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
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uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
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HENVCFG_HADE);
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uint64_t valh = (uint64_t)val << 32;
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RISCVException ret;
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