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Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2009-08-16 11:13:18 +00:00
parent 636aa20056
commit 90e189ece1
12 changed files with 269 additions and 245 deletions
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4
darwin-user/main.c
View File

@ -156,7 +156,7 @@ void cpu_loop(CPUPPCState *env)
/* To deal with multiple qemu header version as host for the darwin-user code */
# define DAR SPR_DAR
#endif
EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* Handle this via the gdb */
gdb_handlesig (env, SIGSEGV);
@ -165,7 +165,7 @@ void cpu_loop(CPUPPCState *env)
queue_signal(info.si_signo, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* Handle this via the gdb */
gdb_handlesig (env, SIGSEGV);

28
hw/ppc.c
View File

@ -795,9 +795,9 @@ static void cpu_4xx_fit_cb (void *opaque)
env->spr[SPR_40x_TSR] |= 1 << 26;
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
/* Programmable interval timer */
@ -841,12 +841,12 @@ static void cpu_4xx_pit_cb (void *opaque)
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
start_stop_pit(env, tb_env, 1);
LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
"%016" PRIx64 "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
"%016" PRIx64 "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
}
/* Watchdog timer */
@ -881,8 +881,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
if (next == now)
next++;
LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
case 0x0:
case 0x1:
@ -924,7 +924,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
LOG_TB("%s val" ADDRX "\n", __func__, val);
LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
ppcemb_timer->pit_reload = val;
start_stop_pit(env, tb_env, 0);
}
@ -936,7 +936,7 @@ target_ulong load_40x_pit (CPUState *env)
void store_booke_tsr (CPUState *env, target_ulong val)
{
LOG_TB("%s: val " ADDRX "\n", __func__, val);
LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
if (val & 0x80000000)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
@ -947,7 +947,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
ppc_tb_t *tb_env;
tb_env = env->tb_env;
LOG_TB("%s: val " ADDRX "\n", __func__, val);
LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
env->spr[SPR_40x_TCR] = val & 0xFFC00000;
start_stop_pit(env, tb_env, 1);
cpu_4xx_wdt_cb(env);

12
hw/ppc405_boards.c
View File

@ -221,8 +221,8 @@ static void ref405ep_init (ram_addr_t ram_size,
bios_offset = qemu_ram_alloc(bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " ADDRX " at offset %08lx "
" addr " ADDRX " '%s' %d\n",
printf("Register parallel flash %d size " TARGET_FMT_lx
" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
@ -536,8 +536,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16;
bios_offset = qemu_ram_alloc(bios_size);
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " ADDRX " at offset %08lx "
" addr " ADDRX " '%s' %d\n",
printf("Register parallel flash %d size " TARGET_FMT_lx
" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
@ -577,8 +577,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
bios_size = 32 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " ADDRX " at offset %08lx "
" addr " ADDRX " '%s'\n",
printf("Register parallel flash %d size " TARGET_FMT_lx
" at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif

70
hw/ppc405_uc.c
View File

@ -267,7 +267,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
opba = opaque;
switch (addr) {
@ -291,7 +291,8 @@ static void opba_writeb (void *opaque,
ppc4xx_opba_t *opba;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba = opaque;
switch (addr) {
@ -311,7 +312,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 8;
ret |= opba_readb(opaque, addr + 1);
@ -323,7 +324,8 @@ static void opba_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba_writeb(opaque, addr, value >> 8);
opba_writeb(opaque, addr + 1, value);
@ -334,7 +336,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = opba_readb(opaque, addr) << 24;
ret |= opba_readb(opaque, addr + 1) << 16;
@ -346,7 +348,8 @@ static void opba_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
opba_writeb(opaque, addr, value >> 24);
opba_writeb(opaque, addr + 1, value >> 16);
@ -380,7 +383,7 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(opba_read, opba_write, opba);
cpu_register_physical_memory(base, 0x002, io);
@ -744,7 +747,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
@ -757,7 +760,8 @@ static void ppc405_gpio_writeb (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
@ -767,7 +771,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
@ -780,7 +784,8 @@ static void ppc405_gpio_writew (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
@ -790,7 +795,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
return 0;
@ -803,7 +808,8 @@ static void ppc405_gpio_writel (void *opaque,
gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
@ -833,7 +839,7 @@ static void ppc405_gpio_init(target_phys_addr_t base)
gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
cpu_register_physical_memory(base, 0x038, io);
@ -1035,7 +1041,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
i2c = opaque;
switch (addr) {
@ -1090,7 +1096,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
break;
}
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
#endif
return ret;
@ -1102,7 +1108,8 @@ static void ppc4xx_i2c_writeb (void *opaque,
ppc4xx_i2c_t *i2c;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
i2c = opaque;
switch (addr) {
@ -1160,7 +1167,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 8;
ret |= ppc4xx_i2c_readb(opaque, addr + 1);
@ -1172,7 +1179,8 @@ static void ppc4xx_i2c_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 8);
ppc4xx_i2c_writeb(opaque, addr + 1, value);
@ -1183,7 +1191,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
uint32_t ret;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
ret = ppc4xx_i2c_readb(opaque, addr) << 24;
ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
@ -1197,7 +1205,8 @@ static void ppc4xx_i2c_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
ppc4xx_i2c_writeb(opaque, addr, value >> 24);
ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
@ -1241,7 +1250,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
cpu_register_physical_memory(base, 0x011, io);
@ -1269,7 +1278,7 @@ struct ppc4xx_gpt_t {
static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
@ -1279,7 +1288,8 @@ static void ppc4xx_gpt_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
/* XXX: generate a bus fault */
}
@ -1287,7 +1297,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
/* XXX: generate a bus fault */
return -1;
@ -1297,7 +1307,8 @@ static void ppc4xx_gpt_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
/* XXX: generate a bus fault */
}
@ -1361,7 +1372,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
int idx;
#ifdef DEBUG_GPT
printf("%s: addr " PADDRX "\n", __func__, addr);
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
gpt = opaque;
switch (addr) {
@ -1416,7 +1427,8 @@ static void ppc4xx_gpt_writel (void *opaque,
int idx;
#ifdef DEBUG_I2C
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
gpt = opaque;
switch (addr) {
@ -1522,7 +1534,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
}
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT
printf("%s: offset " PADDRX "\n", __func__, base);
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
cpu_register_physical_memory(base, 0x0d4, io);

11
hw/ppc4xx_devs.c
View File

@ -235,7 +235,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
uic = opaque;
dcrn -= uic->dcr_base;
LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
@ -368,7 +368,8 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
bcr = 0x000C0000;
break;
default:
printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
ram_size);
return 0x00000000;
}
bcr |= ram_base & 0xFF800000;
@ -401,7 +402,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
if (*bcrp & 0x00000001) {
/* Unmap RAM */
#ifdef DEBUG_SDRAM
printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
#endif
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
@ -410,7 +411,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
*bcrp = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
#ifdef DEBUG_SDRAM
printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(bcr), sdram_size(bcr));
#endif
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
@ -439,7 +440,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
for (i = 0; i < sdram->nbanks; i++) {
#ifdef DEBUG_SDRAM
printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
#endif
cpu_register_physical_memory(sdram_base(sdram->bcr[i]),

36
hw/ppc_prep.c
View File

@ -112,7 +112,10 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
static void _PPC_intack_write (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
#if 0
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
#endif
}
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
@ -121,7 +124,10 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
if ((addr & 0xf) == 0)
retval = pic_intack_read(isa_pic);
// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
#if 0
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
#endif
return retval;
}
@ -191,7 +197,8 @@ static struct {
static void PPC_XCSR_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writew (void *opaque,
@ -200,7 +207,8 @@ static void PPC_XCSR_writew (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writel (void *opaque,
@ -209,14 +217,16 @@ static void PPC_XCSR_writel (void *opaque,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
return retval;
}
@ -225,7 +235,8 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap16(retval);
#endif
@ -237,7 +248,8 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t retval = 0;
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
retval);
#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap32(retval);
#endif
@ -469,7 +481,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap16(value);
#endif
PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outw(NULL, addr, value);
}
@ -483,7 +495,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap16(ret);
#endif
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}
@ -497,7 +509,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
#ifdef TARGET_WORDS_BIGENDIAN
value = bswap32(value);
#endif
PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
cpu_outl(NULL, addr, value);
}
@ -511,7 +523,7 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
#ifdef TARGET_WORDS_BIGENDIAN
ret = bswap32(ret);
#endif
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
return ret;
}

6
linux-user/main.c
View File

@ -1140,7 +1140,7 @@ void cpu_loop(CPUPPCState *env)
"Aborting\n");
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
env->spr[SPR_DAR]);
/* XXX: check this. Seems bugged */
switch (env->error_code & 0xFF000000) {
@ -1172,8 +1172,8 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
env->spr[SPR_SRR0]);
EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
"\n", env->spr[SPR_SRR0]);
/* XXX: check this */
switch (env->error_code & 0xFF000000) {
case 0x40000000:

2
target-ppc/cpu.h
View File

@ -57,8 +57,6 @@
#include "cpu-defs.h"
#define REGX "%016" PRIx64
#define ADDRX TARGET_FMT_lx
#define PADDRX TARGET_FMT_plx
#include <setjmp.h>

213
target-ppc/helper.c
View File

@ -345,8 +345,8 @@ static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
tlb = &env->tlb[nr].tlb6;
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
nr, env->nb_tlb, eaddr);
LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
env->nb_tlb, eaddr);
pte_invalidate(&tlb->pte0);
tlb_flush_page(env, tlb->EPN);
}
@ -371,8 +371,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
tlb = &env->tlb[nr].tlb6;
LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
" PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
/* Invalidate any pending reference in Qemu for this virtual address */
__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
tlb->pte0 = pte0;
@ -397,19 +397,17 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
tlb = &env->tlb[nr].tlb6;
/* This test "emulates" the PTE index match for hardware TLBs */
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX
"] <> " ADDRX "\n",
nr, env->nb_tlb,
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
"] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
continue;
}
LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
" %c %c\n",
nr, env->nb_tlb,
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, eaddr, tlb->pte1,
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, eaddr, tlb->pte1,
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
case -3:
/* TLB inconsistency */
@ -436,8 +434,8 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
}
if (best != -1) {
done:
LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
/* Update page flags */
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
}
@ -479,8 +477,8 @@ static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
int key, pp, valid, prot;
bl = (*BATl & 0x0000003F) << 17;
LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
(uint8_t)(*BATl & 0x0000003F), bl, ~bl);
LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
(uint8_t)(*BATl & 0x0000003F), bl, ~bl);
prot = 0;
valid = (*BATl >> 6) & 1;
if (valid) {
@ -504,8 +502,8 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
int i, valid, prot;
int ret = -1;
LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', virtual);
LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', virtual);
switch (type) {
case ACCESS_CODE:
BATlt = env->IBAT[1];
@ -527,9 +525,9 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
} else {
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
}
LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
" BATl " ADDRX "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
" BATl " TARGET_FMT_lx "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
if ((virtual & 0xF0000000) == BEPIu &&
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
/* BAT matches */
@ -542,7 +540,7 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
ctx->prot = prot;
ret = check_prot(ctx->prot, rw, type);
if (ret == 0)
LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
break;
@ -552,15 +550,16 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
if (ret < 0) {
#if defined(DEBUG_BATS)
if (qemu_log_enabled()) {
LOG_BATS("no BAT match for " ADDRX ":\n", virtual);
LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
for (i = 0; i < 4; i++) {
BATu = &BATut[i];
BATl = &BATlt[i];
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
" BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
" BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
TARGET_FMT_lx " " TARGET_FMT_lx "\n",
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
*BATu, *BATl, BEPIu, BEPIl, bl);
}
@ -594,22 +593,20 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
& TARGET_PAGE_MASK;
r = pte64_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
" %d %d %d " ADDRX "\n",
base + (i * 16), pte0, pte1,
(int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
ctx->ptem);
LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
(int)((pte0 >> 1) & 1), ctx->ptem);
} else
#endif
{
pte0 = ldl_phys(base + (i * 8));
pte1 = ldl_phys(base + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
" %d %d %d " ADDRX "\n",
base + (i * 8), pte0, pte1,
(int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
ctx->ptem);
LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
(int)((pte0 >> 6) & 1), ctx->ptem);
}
switch (r) {
case -3:
@ -637,8 +634,8 @@ static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
}
if (good != -1) {
done:
LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
ctx->raddr, ctx->prot, ret);
LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
ctx->raddr, ctx->prot, ret);
/* Update page flags */
pte1 = ctx->raddr;
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
@ -730,7 +727,7 @@ static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
int n, ret;
ret = -5;
LOG_SLB("%s: eaddr " ADDRX "\n", __func__, eaddr);
LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
mask = 0x0000000000000000ULL; /* Avoid gcc warning */
for (n = 0; n < env->slb_nr; n++) {
ppc_slb_t *slb = slb_get_entry(env, n);
@ -825,7 +822,7 @@ target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
rt = 0;
}
LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
ADDRX "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
return rt;
}
@ -849,9 +846,9 @@ void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
slb->tmp = (vsid << 8) | (flags << 3);
LOG_SLB("%s: %d " ADDRX " - " ADDRX " => %016" PRIx64
" %08" PRIx32 "\n", __func__,
slb_nr, rb, rs, slb->tmp64, slb->tmp);
LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
" %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
slb->tmp);
slb_set_entry(env, slb_nr, slb);
}
@ -909,14 +906,14 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
sdr_sh = 16;
sdr_mask = 0xFFC0;
target_page_bits = TARGET_PAGE_BITS;
LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
" nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip,
env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
rw, type);
LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
TARGET_FMT_lx " lr=" TARGET_FMT_lx
" ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
(int)msr_dr, pr != 0 ? 1 : 0, rw, type);
}
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
ctx->key, ds, ctx->nx, vsid);
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
ctx->key, ds, ctx->nx, vsid);
ret = -1;
if (!ds) {
/* Check if instruction fetch is allowed, if needed */
@ -937,15 +934,14 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
}
mask = (htab_mask << sdr_sh) | sdr_mask;
LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
" mask " PADDRX " " ADDRX "\n",
sdr, sdr_sh, hash, mask, page_mask);
LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
" mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
sdr, sdr_sh, hash, mask, page_mask);
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
/* Secondary table address */
hash = (~hash) & vsid_mask;
LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
" mask " PADDRX "\n",
sdr, sdr_sh, hash, mask);
LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
" mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
@ -968,19 +964,19 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
/* Software TLB search */
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
} else {
LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
"api=" ADDRX " hash=" PADDRX
" pg_addr=" PADDRX "\n",
sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
" pg_addr=" TARGET_FMT_plx "\n",
sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
/* Primary table lookup */
ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
if (ret < 0) {
/* Secondary table lookup */
if (eaddr != 0xEFFFFFFF)
LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
"api=" ADDRX " hash=" PADDRX
" pg_addr=" PADDRX "\n",
sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
"api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
" pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
pgidx, hash, ctx->pg_addr[1]);
ret2 = find_pte(env, ctx, 1, rw, type,
target_page_bits);
if (ret2 != -1)
@ -991,8 +987,8 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
if (qemu_log_enabled()) {
target_phys_addr_t curaddr;
uint32_t a0, a1, a2, a3;
qemu_log("Page table: " PADDRX " len " PADDRX "\n",
sdr, mask + 0x80);
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
"\n", sdr, mask + 0x80);
for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
curaddr += 16) {
a0 = ldl_phys(curaddr);
@ -1000,8 +996,8 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
a2 = ldl_phys(curaddr + 8);
a3 = ldl_phys(curaddr + 12);
if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
qemu_log(PADDRX ": %08x %08x %08x %08x\n",
curaddr, a0, a1, a2, a3);
qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
curaddr, a0, a1, a2, a3);
}
}
}
@ -1066,9 +1062,9 @@ static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
return -1;
}
mask = ~(tlb->size - 1);
LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
" " ADDRX " %u\n",
__func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
" " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
mask, (uint32_t)tlb->PID);
/* Check PID */
if (tlb->PID != 0 && tlb->PID != pid)
return -1;
@ -1191,15 +1187,14 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
}
if (ret >= 0) {
ctx->raddr = raddr;
LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
return 0;
}
}
LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX
" %d %d\n", __func__, address, raddr, ctx->prot,
ret);
LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
" %d %d\n", __func__, address, raddr, ctx->prot, ret);
return ret;
}
@ -1382,8 +1377,8 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
}
}
#if 0
qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
__func__, eaddr, ret, ctx->raddr);
qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
__func__, eaddr, ret, ctx->raddr);
#endif
return ret;
@ -1670,8 +1665,8 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
base = BATu & ~0x0001FFFF;
end = base + mask + 0x00020000;
LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
base, end, mask);
LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
TARGET_FMT_lx ")\n", base, end, mask);
for (page = base; page != end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
LOG_BATS("Flush done\n");
@ -1681,8 +1676,8 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
target_ulong value)
{
LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
nr, ul == 0 ? 'u' : 'l', value, env->nip);
}
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
@ -1952,7 +1947,7 @@ void ppc_store_asr (CPUPPCState *env, target_ulong value)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
{
LOG_MMU("%s: " ADDRX "\n", __func__, value);
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
if (env->sdr1 != value) {
/* XXX: for PowerPC 64, should check that the HTABSIZE value
* is <= 28
@ -1972,8 +1967,8 @@ target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
{
LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
__func__, srnum, value, env->sr[srnum]);
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
uint64_t rb = 0, rs = 0;
@ -2037,9 +2032,10 @@ void ppc_hw_interrupt (CPUState *env)
static inline void dump_syscall(CPUState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX
" r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip);
" r5=" REGX " r6=" REGX " nip=" TARGET_FMT_lx "\n",
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
ppc_dump_gpr(env, 6), env->nip);
}
/* Note that this function should be greatly optimized
@ -2061,8 +2057,8 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
lpes1 = 1;
}
qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n",
env->nip, excp, env->error_code);
qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
" => %08x (%02x)\n", env->nip, excp, env->error_code);
msr = env->msr;
new_msr = msr;
srr0 = SPR_SRR0;
@ -2129,15 +2125,15 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
}
goto store_next;
case POWERPC_EXCP_DSI: /* Data storage exception */
LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
env->spr[SPR_DSISR], env->spr[SPR_DAR]);
LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
msr, env->nip);
LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
"\n", msr, env->nip);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
@ -2174,8 +2170,7 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
msr |= 0x00010000;
break;
case POWERPC_EXCP_INVAL:
LOG_EXCP("Invalid instruction at " ADDRX "\n",
env->nip);
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
@ -2449,11 +2444,11 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
miss = &env->spr[SPR_DMISS];
cmp = &env->spr[SPR_DCMP];
}
qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
" H1 " ADDRX " H2 " ADDRX " %08x\n",
es, en, *miss, en, *cmp,
env->spr[SPR_HASH1], env->spr[SPR_HASH2],
env->error_code);
qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
env->spr[SPR_HASH1], env->spr[SPR_HASH2],
env->error_code);
}
#endif
msr |= env->crf[0] << 28;
@ -2482,9 +2477,9 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
miss = &env->spr[SPR_TLBMISS];
cmp = &env->spr[SPR_PTEHI];
}
qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
" %08x\n",
es, en, *miss, en, *cmp, env->error_code);
qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
env->error_code);
}
#endif
msr |= env->error_code; /* key bit */
@ -2748,8 +2743,8 @@ void ppc_hw_interrupt (CPUPPCState *env)
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
{
qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n",
RA, msr);
qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
TARGET_FMT_lx "\n", RA, msr);
}
void cpu_ppc_reset (void *opaque)

70
target-ppc/op_helper.c
View File

@ -56,14 +56,14 @@ void helper_raise_exception (uint32_t exception)
/* SPR accesses */
void helper_load_dump_spr (uint32_t sprn)
{
qemu_log("Read SPR %d %03x => " ADDRX "\n",
sprn, sprn, env->spr[sprn]);
qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
void helper_store_dump_spr (uint32_t sprn)
{
qemu_log("Write SPR %d %03x <= " ADDRX "\n",
sprn, sprn, env->spr[sprn]);
qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
env->spr[sprn]);
}
target_ulong helper_load_tbl (void)
@ -160,8 +160,8 @@ void helper_store_hid0_601 (target_ulong val)
env->hflags_nmsr &= ~(1 << MSR_LE);
env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
env->hflags |= env->hflags_nmsr;
qemu_log("%s: set endianness to %c => " ADDRX "\n",
__func__, val & 0x8 ? 'l' : 'b', env->hflags);
qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
val & 0x8 ? 'l' : 'b', env->hflags);
}
env->spr[SPR_HID0] = (uint32_t)val;
}
@ -3804,9 +3804,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code)
EPN = env->spr[SPR_DMISS];
}
way = (env->spr[SPR_SRR1] >> 17) & 1;
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
RPN, way);
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@ -3832,9 +3832,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code)
CMP = env->spr[SPR_PTEHI];
EPN = env->spr[SPR_TLBMISS] & ~0x3;
way = env->spr[SPR_TLBMISS] & 0x3;
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
" PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP,
RPN, way);
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@ -3958,14 +3958,15 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
ppcemb_tlb_t *tlb;
target_ulong page, end;
LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,
val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@ -3990,18 +3991,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
tlb->attr = val & 0xFF;
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@ -4011,7 +4012,8 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,
val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
tlb->RPN = val & 0xFFFFFC00;
@ -4020,13 +4022,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
tlb->prot |= PAGE_EXEC;
if (val & 0x100)
tlb->prot |= PAGE_WRITE;
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
LOG_SWTLB("%s: set up TLB %d RPN " TARGET_FMT_plx " EPN " TARGET_FMT_lx
" size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
target_ulong helper_4xx_tlbsx (target_ulong address)
@ -4041,8 +4043,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
target_ulong EPN, RPN, size;
int do_flush_tlbs;
LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
__func__, word, (int)entry, value);
LOG_SWTLB("%s word %d entry %d value " TARGET_FMT_lx "\n",
__func__, word, (int)entry, value);
do_flush_tlbs = 0;
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;

58
target-ppc/translate.c
View File

@ -3755,17 +3755,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
*/
if (sprn != SPR_PVR) {
qemu_log("Trying to read privileged spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
sprn, sprn, ctx->nip);
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to read privileged spr %d %03x at "
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
}
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
/* Not defined */
qemu_log("Trying to read invalid spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
}
@ -3905,16 +3905,16 @@ static void gen_mtspr(DisasContext *ctx)
} else {
/* Privilege exception */
qemu_log("Trying to write privileged spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
sprn, sprn, ctx->nip);
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
"\n", sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
/* Not defined */
qemu_log("Trying to write invalid spr %d %03x at "
ADDRX "\n", sprn, sprn, ctx->nip);
printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
sprn, sprn, ctx->nip);
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
}
@ -8839,10 +8839,12 @@ void cpu_dump_state (CPUState *env, FILE *f,
int i;
cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
env->nip, env->lr, env->ctr, env->xer);
cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
TARGET_FMT_lx " XER %08x\n", env->nip, env->lr, env->ctr,
env->xer);
cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
env->hflags, env->mmu_idx);
#if !defined(NO_TIMER_DUMP)
cpu_fprintf(f, "TB %08x %08x "
#if !defined(CONFIG_USER_ONLY)
@ -8876,7 +8878,8 @@ void cpu_dump_state (CPUState *env, FILE *f,
a = 'E';
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
}
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve_addr);
cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
env->reserve_addr);
for (i = 0; i < 32; i++) {
if ((i & (RFPL - 1)) == 0)
cpu_fprintf(f, "FPR%02d", i);
@ -8886,8 +8889,9 @@ void cpu_dump_state (CPUState *env, FILE *f,
}
cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
#if !defined(CONFIG_USER_ONLY)
cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
cpu_fprintf(f, "SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " SDR1 "
TARGET_FMT_lx "\n", env->spr[SPR_SRR0], env->spr[SPR_SRR1],
env->sdr1);
#endif
#undef RGPL
@ -9016,7 +9020,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
gen_opc_icount[lj] = num_insns;
}
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
@ -9044,12 +9048,12 @@ static inline void gen_intermediate_code_internal(CPUState *env,
if (unlikely(handler->handler == &gen_invalid)) {
if (qemu_log_enabled()) {
qemu_log("invalid/unsupported opcode: "
"%02x - %02x - %02x (%08x) " ADDRX " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
} else {
printf("invalid/unsupported opcode: "
"%02x - %02x - %02x (%08x) " ADDRX " %d\n",
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
}
@ -9057,13 +9061,13 @@ static inline void gen_intermediate_code_internal(CPUState *env,
if (unlikely((ctx.opcode & handler->inval) != 0)) {
if (qemu_log_enabled()) {
qemu_log("invalid bits: %08x for opcode: "
"%02x - %02x - %02x (%08x) " ADDRX "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);
} else {
printf("invalid bits: %08x for opcode: "
"%02x - %02x - %02x (%08x) " ADDRX "\n",
"%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
ctx.opcode & handler->inval, opc1(ctx.opcode),
opc2(ctx.opcode), opc3(ctx.opcode),
ctx.opcode, ctx.nip - 4);

4
target-ppc/translate_init.c
View File

@ -543,8 +543,8 @@ static inline void spr_register (CPUPPCState *env, int num,
exit(1);
}
#if defined(PPC_DEBUG_SPR)
printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
initial_value);
printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
name, initial_value);
#endif
spr->name = name;
spr->uea_read = uea_read;