OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/ppc: implement vsrq

Browse Source 
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-22-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 committed by Cédric Le Goater
parent 3e39edb688
commit 946c3491c6
2 changed files with 31 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/ppc/insn32.decode
View File

@ -479,6 +479,7 @@ VSRB 000100 ..... ..... ..... 01000000100 @VX
VSRH 000100 ..... ..... ..... 01001000100 @VX
VSRW 000100 ..... ..... ..... 01010000100 @VX
VSRD 000100 ..... ..... ..... 11011000100 @VX
VSRQ 000100 ..... ..... ..... 01000000101 @VX
VSRAB 000100 ..... ..... ..... 01100000100 @VX
VSRAH 000100 ..... ..... ..... 01101000100 @VX

40
target/ppc/translate/vmx-impl.c.inc
View File

@ -834,11 +834,10 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
{
TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
n = tcg_temp_new_i64();
@ -852,19 +851,37 @@ static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
get_avr64(n, a->vrb, true);
tcg_gen_andi_i64(t0, n, 64);
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
if (right) {
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, zero, hi);
} else {
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
}
tcg_gen_andi_i64(n, n, 0x3F);
tcg_gen_shl_i64(t0, lo, n);
set_avr64(a->vrt, t0, false);
if (right) {
tcg_gen_shr_i64(t0, hi, n);
} else {
tcg_gen_shl_i64(t0, lo, n);
}
set_avr64(a->vrt, t0, right);
tcg_gen_shl_i64(hi, hi, n);
if (right) {
tcg_gen_shr_i64(lo, lo, n);
} else {
tcg_gen_shl_i64(hi, hi, n);
}
tcg_gen_xori_i64(n, n, 63);
tcg_gen_shr_i64(lo, lo, n);
tcg_gen_shri_i64(lo, lo, 1);
if (right) {
tcg_gen_shl_i64(hi, hi, n);
tcg_gen_shli_i64(hi, hi, 1);
} else {
tcg_gen_shr_i64(lo, lo, n);
tcg_gen_shri_i64(lo, lo, 1);
}
tcg_gen_or_i64(hi, hi, lo);
set_avr64(a->vrt, hi, true);
set_avr64(a->vrt, hi, !right);
tcg_temp_free_i64(hi);
tcg_temp_free_i64(lo);
@ -874,6 +891,9 @@ static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
return true;
}
TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false);
TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true);
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \