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mask all interrupts when MASTER_DISABLE is set 

The MASTER_DISABLE bit (aka mask-all) masks all the interrupts.

According to Sun-4M System Architecture
"The level–15 interrupt sources [...] are maskable with the Interrupt Target
Mask Register. While these interrupts are considered ’non–maskable’ within
the SPARC IU, a mask capability is provided to allow the boot firmware
to establish a basic environment before receiving any level–15 interrupts,
which are non–maskable within SPARC. A mask–all bit is provided to allow
disabling of all external interrupts during change of the CIT."

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Artyom Tarasenko 2010-06-21 20:23:21 +02:00 committed by Blue Swirl
parent 3a5c16fcb8
commit 94c5f455d3
1 changed files with 6 additions and 3 deletions
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9
hw/slavio_intctl.c
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@ -289,9 +289,12 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
}
}
/* Level 15 and CPU timer interrupts are not maskable */
pil_pending |= s->slaves[i].intreg_pending &
(CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
/* Level 15 and CPU timer interrupts are only masked when
the MASTER_DISABLE bit is set */
if (!(s->intregm_disabled & MASTER_DISABLE)) {
pil_pending |= s->slaves[i].intreg_pending &
(CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
}
/* Add soft interrupts */
pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;