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tcg: Allow target-specific implementation of NAND.

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Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson 2010-03-19 13:03:58 -07:00 committed by Aurelien Jarno
parent 8d625cf1d1
commit 9940a96bc8
10 changed files with 29 additions and 0 deletions
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1
tcg/arm/tcg-target.h
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@ -68,6 +68,7 @@ enum {
#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
#define TCG_TARGET_HAS_GUEST_BASE

1
tcg/i386/tcg-target.h
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@ -58,6 +58,7 @@ enum {
// #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
#define TCG_TARGET_HAS_GUEST_BASE

1
tcg/mips/tcg-target.h
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@ -88,6 +88,7 @@ enum {
#undef TCG_TARGET_HAS_andc_i32
#undef TCG_TARGET_HAS_orc_i32
#undef TCG_TARGET_HAS_eqv_i32
#undef TCG_TARGET_HAS_nand_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, zero, rt */

1
tcg/ppc/tcg-target.h
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@ -90,6 +90,7 @@ enum {
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
#define TCG_AREG0 TCG_REG_R27

2
tcg/ppc64/tcg-target.h
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@ -81,6 +81,7 @@ enum {
/* #define TCG_TARGET_HAS_andc_i32 */
/* #define TCG_TARGET_HAS_orc_i32 */
/* #define TCG_TARGET_HAS_eqv_i32 */
/* #define TCG_TARGET_HAS_nand_i32 */
#define TCG_TARGET_HAS_div_i64
/* #define TCG_TARGET_HAS_rot_i64 */
@ -98,6 +99,7 @@ enum {
/* #define TCG_TARGET_HAS_andc_i64 */
/* #define TCG_TARGET_HAS_orc_i64 */
/* #define TCG_TARGET_HAS_eqv_i64 */
/* #define TCG_TARGET_HAS_nand_i64 */
#define TCG_AREG0 TCG_REG_R27

2
tcg/s390/tcg-target.h
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@ -60,6 +60,7 @@ enum {
// #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
// #define TCG_TARGET_HAS_div_i64
// #define TCG_TARGET_HAS_rot_i64
@ -77,6 +78,7 @@ enum {
// #define TCG_TARGET_HAS_andc_i64
// #define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R15

2
tcg/sparc/tcg-target.h
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@ -101,6 +101,7 @@ enum {
#define TCG_TARGET_HAS_andc_i32
#define TCG_TARGET_HAS_orc_i32
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_nand_i32
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div_i64
@ -119,6 +120,7 @@ enum {
#define TCG_TARGET_HAS_andc_i64
#define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i64
#endif
/* Note: must be synced with dyngen-exec.h */

11
tcg/tcg-op.h
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@ -1763,14 +1763,25 @@ static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
#ifdef TCG_TARGET_HAS_nand_i32
tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
#else
tcg_gen_and_i32(ret, arg1, arg2);
tcg_gen_not_i32(ret, ret);
#endif
}
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
#ifdef TCG_TARGET_HAS_nand_i64
tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
#elif defined(TCG_TARGET_HAS_nand_i32) && TCG_TARGET_REG_BITS == 32
tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
#else
tcg_gen_and_i64(ret, arg1, arg2);
tcg_gen_not_i64(ret, ret);
#endif
}
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)

6
tcg/tcg-opc.h
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@ -119,6 +119,9 @@ DEF2(orc_i32, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_eqv_i32
DEF2(eqv_i32, 1, 2, 0, 0)
#endif
#ifdef TCG_TARGET_HAS_nand_i32
DEF2(nand_i32, 1, 2, 0, 0)
#endif
#if TCG_TARGET_REG_BITS == 64
DEF2(mov_i64, 1, 1, 0, 0)
@ -205,6 +208,9 @@ DEF2(orc_i64, 1, 2, 0, 0)
#ifdef TCG_TARGET_HAS_eqv_i64
DEF2(eqv_i64, 1, 2, 0, 0)
#endif
#ifdef TCG_TARGET_HAS_nand_i64
DEF2(nand_i64, 1, 2, 0, 0)
#endif
#endif
/* QEMU specific */

2
tcg/x86_64/tcg-target.h
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@ -86,6 +86,8 @@ enum {
// #define TCG_TARGET_HAS_orc_i64
// #define TCG_TARGET_HAS_eqv_i32
// #define TCG_TARGET_HAS_eqv_i64
// #define TCG_TARGET_HAS_nand_i32
// #define TCG_TARGET_HAS_nand_i64
#define TCG_TARGET_HAS_GUEST_BASE