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target/riscv: Move hstatus.spvp check to check_access_hlsv

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The current cpu_mmu_index value is really irrelevant to
the HLV/HSV lookup.  Provide the correct priv level directly.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2023-04-12 13:43:23 +02:00 committed by Alistair Francis
parent 02369f7906
commit 9de7b7b5c7
2 changed files with 2 additions and 10 deletions
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10
target/riscv/cpu_helper.c
View File

@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
use_background = true;
}
/*
* MPRV does not affect the virtual-machine load/store
* instructions, HLV, HLVX, and HSV.
*/
if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
}
if (first_stage == false) {
/*
* We are in stage 2 translation, this is similar to stage 1.
@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
* instructions, HLV, HLVX, and HSV.
*/
if (mmuidx_2stage(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
;
} else if (mode == PRV_M && access_type != MMU_INST_FETCH &&
get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);

2
target/riscv/op_helper.c
View File

@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra);
}
return cpu_mmu_index(env, x) | MMU_2STAGE_BIT;
return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT;
}
target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)