target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
Rather than increment base_reg and num, compute num from the change to base_reg at the end. Clean up some nearby comments. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int reg_width)
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g_string_append(s, "</union>");
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}
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
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int i, reg_width = (cpu->sve_max_vq * 128);
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info->num = 0;
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int reg_width = cpu->sve_max_vq * 128;
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int base_reg = orig_base_reg;
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int i;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
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/* Create the vector union type. */
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output_vector_union_type(s, reg_width);
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/* Finally the sve prefix type */
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/* Create the predicate vector type. */
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g_string_append_printf(s,
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"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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reg_width / 8);
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/* Then define each register in parts for each vq */
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/* Define the vector registers. */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"z%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svev\"/>",
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i, reg_width, base_reg++);
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info->num++;
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}
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/* fpscr & status registers */
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g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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@ -310,27 +313,29 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
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g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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info->num += 2;
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/* Define the predicate registers. */
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for (i = 0; i < 16; i++) {
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g_string_append_printf(s,
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"<reg name=\"p%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svep\"/>",
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i, cpu->sve_max_vq * 16, base_reg++);
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info->num++;
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}
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g_string_append_printf(s,
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"<reg name=\"ffr\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"svep\"/>",
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cpu->sve_max_vq * 16, base_reg++);
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/* Define the vector length pseudo-register. */
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g_string_append_printf(s,
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"<reg name=\"vg\" bitsize=\"64\""
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" regnum=\"%d\" type=\"int\"/>",
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base_reg++);
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info->num += 2;
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g_string_append_printf(s, "</feature>");
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info->desc = g_string_free(s, false);
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g_string_append_printf(s, "</feature>");
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info->desc = g_string_free(s, false);
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info->num = base_reg - orig_base_reg;
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return info->num;
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}
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