usb: Add basic code to emulate Chipidea USB IP
Add code to emulate Chipidea USB IP (used in i.MX SoCs). Tested to work against: -usb -drive if=none,id=stick,file=usb.img,format=raw -device \ usb-storage,bus=usb-bus.0,drive=stick Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Jason Wang <jasowang@redhat.com> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -12,6 +12,7 @@ common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o
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common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o
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obj-$(CONFIG_TUSB6010) += tusb6010.o
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obj-$(CONFIG_IMX) += chipidea.o
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# emulated usb devices
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common-obj-$(CONFIG_USB) += dev-hub.o
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176
hw/usb/chipidea.c
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176
hw/usb/chipidea.c
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@ -0,0 +1,176 @@
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/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* Chipidea USB block emulation code
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/usb/hcd-ehci.h"
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#include "hw/usb/chipidea.h"
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#include "qemu/log.h"
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enum {
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CHIPIDEA_USBx_DCIVERSION = 0x000,
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CHIPIDEA_USBx_DCCPARAMS = 0x004,
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CHIPIDEA_USBx_DCCPARAMS_HC = BIT(8),
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};
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static uint64_t chipidea_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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return 0;
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}
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static void chipidea_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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}
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static const struct MemoryRegionOps chipidea_ops = {
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.read = chipidea_read,
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.write = chipidea_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the
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* real device but in practice there is no reason for a guest
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* to access this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static uint64_t chipidea_dc_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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switch (offset) {
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case CHIPIDEA_USBx_DCIVERSION:
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return 0x1;
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case CHIPIDEA_USBx_DCCPARAMS:
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/*
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* Real hardware (at least i.MX7) will also report the
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* controller as "Device Capable" (and 8 supported endpoints),
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* but there doesn't seem to be much point in doing so, since
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* we don't emulate that part.
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*/
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return CHIPIDEA_USBx_DCCPARAMS_HC;
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}
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return 0;
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}
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static void chipidea_dc_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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}
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static const struct MemoryRegionOps chipidea_dc_ops = {
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.read = chipidea_dc_read,
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.write = chipidea_dc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void chipidea_init(Object *obj)
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{
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EHCIState *ehci = &SYS_BUS_EHCI(obj)->ehci;
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ChipideaState *ci = CHIPIDEA(obj);
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int i;
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for (i = 0; i < ARRAY_SIZE(ci->iomem); i++) {
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const struct {
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const char *name;
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hwaddr offset;
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uint64_t size;
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const struct MemoryRegionOps *ops;
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} regions[ARRAY_SIZE(ci->iomem)] = {
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/*
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* Registers located between offsets 0x000 and 0xFC
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*/
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{
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.name = TYPE_CHIPIDEA ".misc",
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.offset = 0x000,
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.size = 0x100,
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.ops = &chipidea_ops,
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},
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/*
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* Registers located between offsets 0x1A4 and 0x1DC
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*/
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{
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.name = TYPE_CHIPIDEA ".endpoints",
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.offset = 0x1A4,
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.size = 0x1DC - 0x1A4 + 4,
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.ops = &chipidea_ops,
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},
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/*
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* USB_x_DCIVERSION and USB_x_DCCPARAMS
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*/
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{
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.name = TYPE_CHIPIDEA ".dc",
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.offset = 0x120,
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.size = 8,
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.ops = &chipidea_dc_ops,
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},
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};
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memory_region_init_io(&ci->iomem[i],
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obj,
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regions[i].ops,
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ci,
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regions[i].name,
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regions[i].size);
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memory_region_add_subregion(&ehci->mem,
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regions[i].offset,
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&ci->iomem[i]);
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}
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}
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static void chipidea_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
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/*
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* Offsets used were taken from i.MX7Dual Applications Processor
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* Reference Manual, Rev 0.1, p. 3177, Table 11-59
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*/
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sec->capsbase = 0x100;
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sec->opregbase = 0x140;
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sec->portnr = 1;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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dc->desc = "Chipidea USB Module";
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}
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static const TypeInfo chipidea_info = {
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.name = TYPE_CHIPIDEA,
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.parent = TYPE_SYS_BUS_EHCI,
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.instance_size = sizeof(ChipideaState),
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.instance_init = chipidea_init,
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.class_init = chipidea_class_init,
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};
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static void chipidea_register_type(void)
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{
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type_register_static(&chipidea_info);
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}
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type_init(chipidea_register_type)
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16
include/hw/usb/chipidea.h
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16
include/hw/usb/chipidea.h
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@ -0,0 +1,16 @@
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#ifndef CHIPIDEA_H
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#define CHIPIDEA_H
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#include "hw/usb/hcd-ehci.h"
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typedef struct ChipideaState {
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/*< private >*/
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EHCISysBusState parent_obj;
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MemoryRegion iomem[3];
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} ChipideaState;
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#define TYPE_CHIPIDEA "usb-chipidea"
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#define CHIPIDEA(obj) OBJECT_CHECK(ChipideaState, (obj), TYPE_CHIPIDEA)
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#endif /* CHIPIDEA_H */
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