target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Use an array for the output, rather than separate tcg_res{l,h} variables. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
063e6e4527
commit
a2c4fb8cae
|
@ -7442,10 +7442,10 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
|
|||
bool part = extract32(insn, 14, 1);
|
||||
bool is_q = extract32(insn, 30, 1);
|
||||
int esize = 8 << size;
|
||||
int i, ofs;
|
||||
int i;
|
||||
int datasize = is_q ? 128 : 64;
|
||||
int elements = datasize / esize;
|
||||
TCGv_i64 tcg_res, tcg_resl, tcg_resh;
|
||||
TCGv_i64 tcg_res[2], tcg_ele;
|
||||
|
||||
if (opcode == 0 || (size == 3 && !is_q)) {
|
||||
unallocated_encoding(s);
|
||||
|
@ -7456,37 +7456,39 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
|
|||
return;
|
||||
}
|
||||
|
||||
tcg_resl = tcg_const_i64(0);
|
||||
tcg_resh = is_q ? tcg_const_i64(0) : NULL;
|
||||
tcg_res = tcg_temp_new_i64();
|
||||
tcg_res[0] = tcg_temp_new_i64();
|
||||
tcg_res[1] = is_q ? tcg_temp_new_i64() : NULL;
|
||||
tcg_ele = tcg_temp_new_i64();
|
||||
|
||||
for (i = 0; i < elements; i++) {
|
||||
int o, w;
|
||||
|
||||
switch (opcode) {
|
||||
case 1: /* UZP1/2 */
|
||||
{
|
||||
int midpoint = elements / 2;
|
||||
if (i < midpoint) {
|
||||
read_vec_element(s, tcg_res, rn, 2 * i + part, size);
|
||||
read_vec_element(s, tcg_ele, rn, 2 * i + part, size);
|
||||
} else {
|
||||
read_vec_element(s, tcg_res, rm,
|
||||
read_vec_element(s, tcg_ele, rm,
|
||||
2 * (i - midpoint) + part, size);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 2: /* TRN1/2 */
|
||||
if (i & 1) {
|
||||
read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
|
||||
read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size);
|
||||
} else {
|
||||
read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
|
||||
read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size);
|
||||
}
|
||||
break;
|
||||
case 3: /* ZIP1/2 */
|
||||
{
|
||||
int base = part * elements / 2;
|
||||
if (i & 1) {
|
||||
read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
|
||||
read_vec_element(s, tcg_ele, rm, base + (i >> 1), size);
|
||||
} else {
|
||||
read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
|
||||
read_vec_element(s, tcg_ele, rn, base + (i >> 1), size);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
@ -7494,19 +7496,18 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
|
|||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
ofs = i * esize;
|
||||
if (ofs < 64) {
|
||||
tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
|
||||
tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
|
||||
w = (i * esize) / 64;
|
||||
o = (i * esize) % 64;
|
||||
if (o == 0) {
|
||||
tcg_gen_mov_i64(tcg_res[w], tcg_ele);
|
||||
} else {
|
||||
tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
|
||||
tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
|
||||
tcg_gen_shli_i64(tcg_ele, tcg_ele, o);
|
||||
tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele);
|
||||
}
|
||||
}
|
||||
|
||||
write_vec_element(s, tcg_resl, rd, 0, MO_64);
|
||||
if (is_q) {
|
||||
write_vec_element(s, tcg_resh, rd, 1, MO_64);
|
||||
for (i = 0; i <= is_q; ++i) {
|
||||
write_vec_element(s, tcg_res[i], rd, i, MO_64);
|
||||
}
|
||||
clear_vec_high(s, is_q, rd);
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue