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Hexagon (target/hexagon) fix l2fetch instructions 

Y4_l2fetch == l2fetch(Rs32, Rt32)
Y5_l2fetch == l2fetch(Rs32, Rtt32)

The semantics for these instructions are present, but the encodings
are missing.

Note that these are treated as nops in qemu, so we add overrides.

Test case added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2021-06-01 18:19:42 -05:00
parent 07c0f65385
commit a5a8d98c85
3 changed files with 23 additions and 0 deletions
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11
target/hexagon/gen_tcg.h
View File

@ -734,4 +734,15 @@
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
/* Nothing to do for these in qemu, need to suppress compiler warnings */
#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
do { \
RsV = RsV; \
RtV = RtV; \
} while (0)
#define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
do { \
RsV = RsV; \
} while (0)
#endif

3
target/hexagon/imported/encode_pp.def
View File

@ -493,6 +493,9 @@ DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss PP------ --------")
DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------")
DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------")
DEF_ENC32(Y4_l2fetch, ICLASS_ST" 011 00 00sssss PP-ttttt 000-----")
DEF_ENC32(Y5_l2fetch, ICLASS_ST" 011 01 00sssss PP-ttttt --------")
/*******************************/
/* */
/* */

9
tests/tcg/hexagon/misc.c
View File

@ -326,6 +326,13 @@ void test_lsbnew(void)
check(result, 5);
}
void test_l2fetch(void)
{
/* These don't do anything in qemu, just make sure they don't assert */
asm volatile ("l2fetch(r0, r1)\n\t"
"l2fetch(r0, r3:2)\n\t");
}
int main()
{
int res;
@ -459,6 +466,8 @@ int main()
test_lsbnew();
test_l2fetch();
puts(err ? "FAIL" : "PASS");
return err;
}