Hexagon (target/hexagon) fix l2fetch instructions
Y4_l2fetch == l2fetch(Rs32, Rt32) Y5_l2fetch == l2fetch(Rs32, Rtt32) The semantics for these instructions are present, but the encodings are missing. Note that these are treated as nops in qemu, so we add overrides. Test case added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1622589584-22571-3-git-send-email-tsimpson@quicinc.com>
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@ -734,4 +734,15 @@
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#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
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#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
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gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
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gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
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/* Nothing to do for these in qemu, need to suppress compiler warnings */
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#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
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do { \
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RsV = RsV; \
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RtV = RtV; \
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} while (0)
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#define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
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do { \
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RsV = RsV; \
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} while (0)
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#endif
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#endif
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@ -493,6 +493,9 @@ DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss PP------ --------")
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DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------")
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DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------")
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DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------")
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DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------")
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DEF_ENC32(Y4_l2fetch, ICLASS_ST" 011 00 00sssss PP-ttttt 000-----")
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DEF_ENC32(Y5_l2fetch, ICLASS_ST" 011 01 00sssss PP-ttttt --------")
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/*******************************/
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/*******************************/
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/* */
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/* */
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/* */
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/* */
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@ -326,6 +326,13 @@ void test_lsbnew(void)
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check(result, 5);
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check(result, 5);
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}
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}
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void test_l2fetch(void)
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{
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/* These don't do anything in qemu, just make sure they don't assert */
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asm volatile ("l2fetch(r0, r1)\n\t"
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"l2fetch(r0, r3:2)\n\t");
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}
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int main()
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int main()
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{
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{
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int res;
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int res;
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@ -459,6 +466,8 @@ int main()
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test_lsbnew();
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test_lsbnew();
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test_l2fetch();
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puts(err ? "FAIL" : "PASS");
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puts(err ? "FAIL" : "PASS");
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return err;
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return err;
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}
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}
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