target/i386: Add support for AVX-IFMA in CPUID enumeration
AVX-IFMA is a new instruction in the latest Intel platform Sierra Forest. This instruction packed multiplies unsigned 52-bit integers and adds the low/high 52-bit products to Qword Accumulators. The bit definition: CPUID.(EAX=7,ECX=1):EAX[bit 23] Add CPUID definition for AVX-IFMA. Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com> Signed-off-by: Tao Su <tao1.su@linux.intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-Id: <20230303065913.1246327-4-tao1.su@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -879,7 +879,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, "fzrm", "fsrs",
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NULL, NULL, "fzrm", "fsrs",
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"fsrc", NULL, NULL, NULL,
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"fsrc", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, "amx-fp16", NULL, NULL,
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NULL, "amx-fp16", NULL, "avx-ifma",
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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},
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@ -917,6 +917,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_FSRC (1U << 12)
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#define CPUID_7_1_EAX_FSRC (1U << 12)
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/* Support Tile Computational Operations on FP16 Numbers */
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/* Support Tile Computational Operations on FP16 Numbers */
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#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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/* Support for VPMADD52[H,L]UQ */
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#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
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/* XFD Extend Feature Disabled */
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/* XFD Extend Feature Disabled */
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#define CPUID_D_1_EAX_XFD (1U << 4)
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#define CPUID_D_1_EAX_XFD (1U << 4)
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