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ppc-7.0 queue : 

* Removal of user-created PHB devices
 * Avocado fixes for --disable-tcg
 * Instruction and Radix MMU fixes
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Merge tag 'pull-ppc-20220314' of https://github.com/legoater/qemu into staging

ppc-7.0 queue :

* Removal of user-created PHB devices
* Avocado fixes for --disable-tcg
* Instruction and Radix MMU fixes

# gpg: Signature made Mon 14 Mar 2022 15:16:07 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20220314' of https://github.com/legoater/qemu:
  ppc/pnv: Remove user-created PHB{3,4,5} devices
  ppc/pnv: Always create the PHB5 PEC devices
  ppc/pnv: Introduce a pnv-phb5 device to match root port
  ppc/xive2: Make type Xive2EndSource not user creatable
  target/ppc: fix xxspltw for big endian hosts
  target/ppc: fix ISI fault cause for Radix MMU
  avocado/ppc_virtex_ml507.py: check TCG accel in test_ppc_virtex_ml507()
  avocado/ppc_prep_40p.py: check TCG accel in all tests
  avocado/ppc_mpc8544ds.py: check TCG accel in test_ppc_mpc8544ds()
  avocado/ppc_bamboo.py: check TCG accel in test_ppc_bamboo()
  avocado/ppc_74xx.py: check TCG accel for all tests
  avocado/ppc_405.py: check TCG accel in test_ppc_ref405ep()
  avocado/ppc_405.py: remove test_ppc_taihu()
  avocado/boot_linux_console.py: check TCG accel in test_ppc_mac99()
  avocado/boot_linux_console.py: check TCG accel in test_ppc_g3beige()
  avocado/replay_kernel.py: make tcg-icount check in run_vm()
  avocado/boot_linux_console.py: check tcg accel in test_ppc64_e500
  avocado/boot_linux_console.py: check for tcg in test_ppc_powernv8/9
  qtest/meson.build: check CONFIG_TCG for boot-serial-test in qtests_ppc
  qtest/meson.build: check CONFIG_TCG for prom-env-test in qtests_ppc

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-03-15 11:27:19 +00:00
parent a72ada1662 9c10d86fee
commit ac621d40b5
21 changed files with 131 additions and 136 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/intc/xive2.c
View File

@ -1000,6 +1000,7 @@ static void xive2_end_source_class_init(ObjectClass *klass, void *data)
dc->desc = "XIVE END Source";
device_class_set_props(dc, xive2_end_source_properties);
dc->realize = xive2_end_source_realize;
dc->user_creatable = false;
}
static const TypeInfo xive2_end_source_info = {

33
hw/pci-host/pnv_phb3.c
View File

@ -994,30 +994,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
int i;
/* User created devices */
if (!phb->chip) {
Error *local_err = NULL;
BusState *s;
phb->chip = pnv_get_chip(pnv, phb->chip_id);
if (!phb->chip) {
error_setg(errp, "invalid chip id: %d", phb->chip_id);
return;
}
/*
* Reparent user created devices to the chip to build
* correctly the device tree.
*/
pnv_chip_parent_fixup(phb->chip, OBJECT(phb), phb->phb_id);
s = qdev_get_parent_bus(DEVICE(phb->chip));
if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) {
error_propagate(errp, local_err);
return;
}
}
if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) {
error_setg(errp, "invalid PHB index: %d", phb->phb_id);
return;
@ -1077,10 +1053,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
if (defaults_enabled()) {
pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
TYPE_PNV_PHB3_ROOT_PORT);
}
pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB3_ROOT_PORT);
}
void pnv_phb3_update_regions(PnvPHB3 *phb)
@ -1131,7 +1104,7 @@ static void pnv_phb3_class_init(ObjectClass *klass, void *data)
dc->realize = pnv_phb3_realize;
device_class_set_props(dc, pnv_phb3_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = true;
dc->user_creatable = false;
}
static const TypeInfo pnv_phb3_type_info = {
@ -1201,7 +1174,7 @@ static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data)
device_class_set_parent_realize(dc, pnv_phb3_root_port_realize,
&rpc->parent_realize);
dc->user_creatable = true;
dc->user_creatable = false;
k->vendor_id = PCI_VENDOR_ID_IBM;
k->device_id = 0x03dc;

69
hw/pci-host/pnv_phb4.c
View File

@ -1545,70 +1545,14 @@ static void pnv_phb4_instance_init(Object *obj)
object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE);
}
static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
int chip_id = phb->chip_id;
int index = phb->phb_id;
int i, j;
for (i = 0; i < chip->num_pecs; i++) {
/*
* For each PEC, check the amount of phbs it supports
* and see if the given phb4 index matches an index.
*/
PnvPhb4PecState *pec = &chip9->pecs[i];
for (j = 0; j < pec->num_phbs; j++) {
if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
return pec;
}
}
}
error_setg(errp,
"pnv-phb4 chip-id %d index %d didn't match any existing PEC",
chip_id, index);
return NULL;
}
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XiveSource *xsrc = &phb->xsrc;
BusState *s;
Error *local_err = NULL;
int nr_irqs;
char name[32];
if (!chip) {
error_setg(errp, "invalid chip id: %d", phb->chip_id);
return;
}
/* User created PHBs need to be assigned to a PEC */
if (!phb->pec) {
phb->pec = pnv_phb4_get_pec(chip, phb, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
}
/* Reparent the PHB to the chip to build the device tree */
pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id);
s = qdev_get_parent_bus(DEVICE(chip));
if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) {
error_propagate(errp, local_err);
return;
}
/* Set the "big_phb" flag */
phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3;
@ -1766,7 +1710,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data)
dc->realize = pnv_phb4_realize;
device_class_set_props(dc, pnv_phb4_properties);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->user_creatable = true;
dc->user_creatable = false;
xfc->notify = pnv_phb4_xive_notify;
}
@ -1783,6 +1727,12 @@ static const TypeInfo pnv_phb4_type_info = {
}
};
static const TypeInfo pnv_phb5_type_info = {
.name = TYPE_PNV_PHB5,
.parent = TYPE_PNV_PHB4,
.instance_size = sizeof(PnvPHB4),
};
static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
@ -1858,7 +1808,7 @@ static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data)
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
dc->desc = "IBM PHB4 PCIE Root Port";
dc->user_creatable = true;
dc->user_creatable = false;
device_class_set_parent_realize(dc, pnv_phb4_root_port_realize,
&rpc->parent_realize);
@ -1888,7 +1838,7 @@ static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->desc = "IBM PHB5 PCIE Root Port";
dc->user_creatable = true;
dc->user_creatable = false;
k->vendor_id = PCI_VENDOR_ID_IBM;
k->device_id = PNV_PHB5_DEVICE_ID;
@ -1907,6 +1857,7 @@ static void pnv_phb4_register_types(void)
type_register_static(&pnv_phb5_root_port_info);
type_register_static(&pnv_phb4_root_port_info);
type_register_static(&pnv_phb4_type_info);
type_register_static(&pnv_phb5_type_info);
type_register_static(&pnv_phb4_iommu_memory_region_info);
}

16
hw/pci-host/pnv_phb4_pec.c
View File

@ -116,9 +116,11 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
int stack_no,
Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4));
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type));
int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb));
object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
&error_abort);
object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
@ -131,9 +133,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
}
/* Add a single Root port if running with defaults */
pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb),
PNV_PHB4_PEC_GET_CLASS(pec)->rp_model);
pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model);
}
static void pnv_pec_realize(DeviceState *dev, Error **errp)
@ -151,10 +151,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
pec->num_phbs = pecc->num_phbs[pec->index];
/* Create PHBs if running with defaults */
if (defaults_enabled()) {
for (i = 0; i < pec->num_phbs; i++) {
pnv_pec_default_phb_realize(pec, i, errp);
}
for (i = 0; i < pec->num_phbs; i++) {
pnv_pec_default_phb_realize(pec, i, errp);
}
/* Initialize the XSCOM regions for the PEC registers */
@ -265,6 +263,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data)
pecc->stk_compat = stk_compat;
pecc->stk_compat_size = sizeof(stk_compat);
pecc->version = PNV_PHB4_VERSION;
pecc->phb_type = TYPE_PNV_PHB4;
pecc->num_phbs = pnv_pec_num_phbs;
pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
}
@ -317,6 +316,7 @@ static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
pecc->stk_compat = stk_compat;
pecc->stk_compat_size = sizeof(stk_compat);
pecc->version = PNV_PHB5_VERSION;
pecc->phb_type = TYPE_PNV_PHB5;
pecc->num_phbs = pnv_phb5_pec_num_stacks;
pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
}

29
hw/ppc/pnv.c
View File

@ -1141,9 +1141,7 @@ static void pnv_chip_power8_instance_init(Object *obj)
object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
if (defaults_enabled()) {
chip8->num_phbs = pcc->num_phbs;
}
chip8->num_phbs = pcc->num_phbs;
for (i = 0; i < chip8->num_phbs; i++) {
object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
@ -1600,9 +1598,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
if (defaults_enabled()) {
chip->num_pecs = pcc->num_pecs;
}
chip->num_pecs = pcc->num_pecs;
for (i = 0; i < chip->num_pecs; i++) {
object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
@ -1976,23 +1972,6 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
return NULL;
}
void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index)
{
Object *parent = OBJECT(chip);
g_autofree char *default_id =
g_strdup_printf("%s[%d]", object_get_typename(obj), index);
if (obj->parent == parent) {
return;
}
object_ref(obj);
object_unparent(obj);
object_property_add_child(
parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj);
object_unref(obj);
}
PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
{
int i;
@ -2132,8 +2111,6 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB3);
}
static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
@ -2152,8 +2129,6 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->dt_power_mgt = pnv_dt_power_mgt;
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4);
}
static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)

5
include/hw/pci-host/pnv_phb4.h
View File

@ -203,6 +203,7 @@ struct PnvPhb4PecClass {
const char *stk_compat;
int stk_compat_size;
uint64_t version;
const char *phb_type;
const uint32_t *num_phbs;
const char *rp_model;
};
@ -211,6 +212,10 @@ struct PnvPhb4PecClass {
* POWER10 definitions
*/
#define TYPE_PNV_PHB5 "pnv-phb5"
#define PNV_PHB5(obj) \
OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5)
#define PNV_PHB5_VERSION 0x000000a500000001ull
#define PNV_PHB5_DEVICE_ID 0x0652

1
include/hw/ppc/pnv.h
View File

@ -190,7 +190,6 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
void pnv_phb_attach_root_port(PCIHostState *pci, const char *name);
void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;

3
target/ppc/mmu-radix64.c
View File

@ -204,7 +204,8 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type,
/* Check if requested access type is allowed */
need_prot = prot_for_access_type(access_type);
if (need_prot & ~*prot) { /* Page Protected for that Access */
*fault_cause |= DSISR_PROTFAULT;
*fault_cause |= access_type == MMU_INST_FETCH ? SRR1_NOEXEC_GUARD :
DSISR_PROTFAULT;
return true;
}

2
target/ppc/translate/vsx-impl.c.inc
View File

@ -1552,7 +1552,7 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim2 *a)
tofs = vsr_full_offset(a->xt);
bofs = vsr_full_offset(a->xb);
bofs += a->uim << MO_32;
#ifndef HOST_WORDS_BIG_ENDIAN
#ifndef HOST_WORDS_BIGENDIAN
bofs ^= 8 | 4;
#endif

17
tests/avocado/boot_linux_console.py
View File

@ -1165,11 +1165,14 @@ class BootLinuxConsole(LinuxKernelTest):
:avocado: tags=arch:ppc64
:avocado: tags=machine:ppce500
:avocado: tags=cpu:e5500
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
tar_hash = '6951d86d644b302898da2fd701739c9406527fe1'
self.do_test_advcal_2018('19', tar_hash, 'uImage')
def do_test_ppc64_powernv(self, proc):
self.require_accelerator("tcg")
images_url = ('https://github.com/open-power/op-build/releases/download/v2.7/')
kernel_url = images_url + 'zImage.epapr'
@ -1194,6 +1197,7 @@ class BootLinuxConsole(LinuxKernelTest):
"""
:avocado: tags=arch:ppc64
:avocado: tags=machine:powernv8
:avocado: tags=accel:tcg
"""
self.do_test_ppc64_powernv('P8')
@ -1201,6 +1205,7 @@ class BootLinuxConsole(LinuxKernelTest):
"""
:avocado: tags=arch:ppc64
:avocado: tags=machine:powernv9
:avocado: tags=accel:tcg
"""
self.do_test_ppc64_powernv('P9')
@ -1208,7 +1213,13 @@ class BootLinuxConsole(LinuxKernelTest):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:g3beige
:avocado: tags=accel:tcg
"""
# TODO: g3beige works with kvm_pr but we don't have a
# reliable way ATM (e.g. looking at /proc/modules) to detect
# whether we're running kvm_hv or kvm_pr. For now let's
# disable this test if we don't have TCG support.
self.require_accelerator("tcg")
tar_hash = 'e0b872a5eb8fdc5bed19bd43ffe863900ebcedfc'
self.vm.add_args('-M', 'graphics=off')
self.do_test_advcal_2018('15', tar_hash, 'invaders.elf')
@ -1217,7 +1228,13 @@ class BootLinuxConsole(LinuxKernelTest):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:mac99
:avocado: tags=accel:tcg
"""
# TODO: mac99 works with kvm_pr but we don't have a
# reliable way ATM (e.g. looking at /proc/modules) to detect
# whether we're running kvm_hv or kvm_pr. For now let's
# disable this test if we don't have TCG support.
self.require_accelerator("tcg")
tar_hash = 'e0b872a5eb8fdc5bed19bd43ffe863900ebcedfc'
self.vm.add_args('-M', 'graphics=off')
self.do_test_advcal_2018('15', tar_hash, 'invaders.elf')

10
tests/avocado/ppc_405.py
View File

@ -25,18 +25,12 @@ class Ppc405Machine(QemuSystemTest):
wait_for_console_pattern(self, 'AMCC PPC405EP Evaluation Board')
exec_command_and_wait_for_pattern(self, 'reset', 'AMCC PowerPC 405EP')
def test_ppc_taihu(self):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:taihu
:avocado: tags=cpu:405ep
"""
self.do_test_ppc405()
def test_ppc_ref405ep(self):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:ref405ep
:avocado: tags=cpu:405ep
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
self.do_test_ppc405()

13
tests/avocado/ppc_74xx.py
View File

@ -11,6 +11,7 @@ from avocado_qemu import wait_for_console_pattern
class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=arch:ppc
:avocado: tags=accel:tcg
"""
timeout = 5
@ -18,6 +19,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7400
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -27,6 +29,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7410
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -36,6 +39,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7441
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -45,6 +49,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7445
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -54,6 +59,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7447
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -63,6 +69,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7447a
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -72,6 +79,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7448
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -81,6 +89,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7450
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -90,6 +99,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7451
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -99,6 +109,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7455
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -108,6 +119,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7457
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')
@ -117,6 +129,7 @@ class ppc74xxCpu(QemuSystemTest):
"""
:avocado: tags=cpu:7457a
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, '>> OpenBIOS')

2
tests/avocado/ppc_bamboo.py
View File

@ -20,7 +20,9 @@ class BambooMachine(QemuSystemTest):
:avocado: tags=machine:bamboo
:avocado: tags=cpu:440epb
:avocado: tags=device:rtl8139
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
tar_url = ('http://landley.net/aboriginal/downloads/binaries/'
'system-image-powerpc-440fp.tar.gz')
tar_hash = '53e5f16414b195b82d2c70272f81c2eedb39bad9'

2
tests/avocado/ppc_mpc8544ds.py
View File

@ -19,7 +19,9 @@ class Mpc8544dsMachine(QemuSystemTest):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:mpc8544ds
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
tar_url = ('https://www.qemu-advent-calendar.org'
'/2020/download/day17.tar.gz')
tar_hash = '7a5239542a7c4257aa4d3b7f6ddf08fb6775c494'

6
tests/avocado/ppc_prep_40p.py
View File

@ -28,7 +28,9 @@ class IbmPrep40pMachine(QemuSystemTest):
:avocado: tags=machine:40p
:avocado: tags=os:netbsd
:avocado: tags=slowness:high
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
bios_url = ('http://ftpmirror.your.org/pub/misc/'
'ftp.software.ibm.com/rs6000/firmware/'
'7020-40p/P12H0456.IMG')
@ -51,7 +53,9 @@ class IbmPrep40pMachine(QemuSystemTest):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:40p
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
self.vm.set_console()
self.vm.add_args('-m', '192') # test fw_cfg
@ -65,7 +69,9 @@ class IbmPrep40pMachine(QemuSystemTest):
:avocado: tags=arch:ppc
:avocado: tags=machine:40p
:avocado: tags=os:netbsd
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
drive_url = ('https://archive.netbsd.org/pub/NetBSD-archive/'
'NetBSD-7.1.2/iso/NetBSD-7.1.2-prep.iso')
drive_hash = 'ac6fa2707d888b36d6fa64de6e7fe48e'

2
tests/avocado/ppc_virtex_ml507.py
View File

@ -19,7 +19,9 @@ class VirtexMl507Machine(QemuSystemTest):
"""
:avocado: tags=arch:ppc
:avocado: tags=machine:virtex-ml507
:avocado: tags=accel:tcg
"""
self.require_accelerator("tcg")
tar_url = ('https://www.qemu-advent-calendar.org'
'/2020/download/hippo.tar.gz')
tar_hash = '306b95bfe7d147f125aa176a877e266db8ef914a'

4
tests/avocado/replay_kernel.py
View File

@ -36,6 +36,9 @@ class ReplayKernelBase(LinuxKernelTest):
def run_vm(self, kernel_path, kernel_command_line, console_pattern,
record, shift, args, replay_path):
# icount requires TCG to be available
self.require_accelerator('tcg')
logger = logging.getLogger('replay')
start_time = time.time()
vm = self.get_vm()
@ -243,6 +246,7 @@ class ReplayKernelNormal(ReplayKernelBase):
"""
:avocado: tags=arch:ppc64
:avocado: tags=machine:pseries
:avocado: tags=accel:tcg
"""
kernel_url = ('https://archives.fedoraproject.org/pub/archive'
'/fedora-secondary/releases/29/Everything/ppc64le/os'

4
tests/qtest/meson.build
View File

@ -160,7 +160,9 @@ qtests_ppc = \
(slirp.found() ? ['test-netfilter'] : []) + \
(config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \
(config_all_devices.has_key('CONFIG_M48T59') ? ['m48t59-test'] : []) + \
['boot-order-test', 'prom-env-test', 'boot-serial-test'] \
(config_all_devices.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + \
(config_all_devices.has_key('CONFIG_TCG') ? ['boot-serial-test'] : []) + \
['boot-order-test']
qtests_ppc64 = \
qtests_ppc + \

1
tests/tcg/ppc64/Makefile.target
View File

@ -27,5 +27,6 @@ run-sha512-vector: QEMU_OPTS+=-cpu POWER10
run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
PPC64_TESTS += signal_save_restore_xer
PPC64_TESTS += xxspltw
TESTS += $(PPC64_TESTS)

1
tests/tcg/ppc64le/Makefile.target
View File

@ -25,5 +25,6 @@ run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
PPC64LE_TESTS += mtfsf
PPC64LE_TESTS += signal_save_restore_xer
PPC64LE_TESTS += xxspltw
TESTS += $(PPC64LE_TESTS)

46
tests/tcg/ppc64le/xxspltw.c Normal file
View File

@ -0,0 +1,46 @@
#include <stdio.h>
#include <stdint.h>
#include <inttypes.h>
#include <assert.h>
#define WORD_A 0xAAAAAAAAUL
#define WORD_B 0xBBBBBBBBUL
#define WORD_C 0xCCCCCCCCUL
#define WORD_D 0xDDDDDDDDUL
#define DWORD_HI (WORD_A << 32 | WORD_B)
#define DWORD_LO (WORD_C << 32 | WORD_D)
#define TEST(HI, LO, UIM, RES) \
do { \
union { \
uint64_t u; \
double f; \
} h = { .u = HI }, l = { .u = LO }; \
/* \
* Use a pair of FPRs to load the VSR avoiding insns \
* newer than xxswapd. \
*/ \
asm("xxmrghd 32, %0, %1\n\t" \
"xxspltw 32, 32, %2\n\t" \
"xxmrghd %0, 32, %0\n\t" \
"xxswapd 32, 32\n\t" \
"xxmrghd %1, 32, %1\n\t" \
: "+f" (h.f), "+f" (l.f) \
: "i" (UIM) \
: "v0"); \
printf("xxspltw(0x%016" PRIx64 "%016" PRIx64 ", %d) =" \
" %016" PRIx64 "%016" PRIx64 "\n", HI, LO, UIM, \
h.u, l.u); \
assert(h.u == (RES)); \
assert(l.u == (RES)); \
} while (0)
int main(void)
{
TEST(DWORD_HI, DWORD_LO, 0, WORD_A << 32 | WORD_A);
TEST(DWORD_HI, DWORD_LO, 1, WORD_B << 32 | WORD_B);
TEST(DWORD_HI, DWORD_LO, 2, WORD_C << 32 | WORD_C);
TEST(DWORD_HI, DWORD_LO, 3, WORD_D << 32 | WORD_D);
return 0;
}