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* Last minute s390x fixes before the hard freeze

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* Whiste space clean-up in ui/, display/ and hw/usb/
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Merge tag 'pull-request-2022-11-08' of https://gitlab.com/thuth/qemu into staging

* Last minute s390x fixes before the hard freeze
* Whiste space clean-up in ui/, display/ and hw/usb/

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# gpg: Signature made Tue 08 Nov 2022 06:29:33 EST
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2022-11-08' of https://gitlab.com/thuth/qemu:
  hw/usb: fix tab indentation
  hw/display: fix tab indentation
  ui: fix tab indentation
  s390x/s390-virtio-ccw: Switch off zPCI enhancements on older machines
  Revert "s390x/s390-virtio-ccw: add zpcii-disable machine property"

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2022-11-08 11:34:06 -05:00
commit ade760a2f6
22 changed files with 7372 additions and 7404 deletions
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352
hw/display/blizzard.c
View File

@ -123,14 +123,14 @@ typedef struct {
/* Bytes(!) per pixel */
static const int blizzard_iformat_bpp[0x10] = {
0,
2, /* RGB 5:6:5*/
3, /* RGB 6:6:6 mode 1 */
3, /* RGB 8:8:8 mode 1 */
2, /* RGB 5:6:5*/
3, /* RGB 6:6:6 mode 1 */
3, /* RGB 8:8:8 mode 1 */
0, 0,
4, /* RGB 6:6:6 mode 2 */
4, /* RGB 8:8:8 mode 2 */
0, /* YUV 4:2:2 */
0, /* YUV 4:2:0 */
4, /* RGB 6:6:6 mode 2 */
4, /* RGB 8:8:8 mode 2 */
0, /* YUV 4:2:2 */
0, /* YUV 4:2:0 */
0, 0, 0, 0, 0, 0,
};
@ -281,196 +281,196 @@ static uint16_t blizzard_reg_read(void *opaque, uint8_t reg)
BlizzardState *s = (BlizzardState *) opaque;
switch (reg) {
case 0x00: /* Revision Code */
case 0x00: /* Revision Code */
return 0xa5;
case 0x02: /* Configuration Readback */
return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
case 0x02: /* Configuration Readback */
return 0x83; /* Macrovision OK, CNF[2:0] = 3 */
case 0x04: /* PLL M-Divider */
case 0x04: /* PLL M-Divider */
return (s->pll - 1) | (1 << 7);
case 0x06: /* PLL Lock Range Control */
case 0x06: /* PLL Lock Range Control */
return s->pll_range;
case 0x08: /* PLL Lock Synthesis Control 0 */
case 0x08: /* PLL Lock Synthesis Control 0 */
return s->pll_ctrl & 0xff;
case 0x0a: /* PLL Lock Synthesis Control 1 */
case 0x0a: /* PLL Lock Synthesis Control 1 */
return s->pll_ctrl >> 8;
case 0x0c: /* PLL Mode Control 0 */
case 0x0c: /* PLL Mode Control 0 */
return s->pll_mode;
case 0x0e: /* Clock-Source Select */
case 0x0e: /* Clock-Source Select */
return s->clksel;
case 0x10: /* Memory Controller Activate */
case 0x14: /* Memory Controller Bank 0 Status Flag */
case 0x10: /* Memory Controller Activate */
case 0x14: /* Memory Controller Bank 0 Status Flag */
return s->memenable;
case 0x18: /* Auto-Refresh Interval Setting 0 */
case 0x18: /* Auto-Refresh Interval Setting 0 */
return s->memrefresh & 0xff;
case 0x1a: /* Auto-Refresh Interval Setting 1 */
case 0x1a: /* Auto-Refresh Interval Setting 1 */
return s->memrefresh >> 8;
case 0x1c: /* Power-On Sequence Timing Control */
case 0x1c: /* Power-On Sequence Timing Control */
return s->timing[0];
case 0x1e: /* Timing Control 0 */
case 0x1e: /* Timing Control 0 */
return s->timing[1];
case 0x20: /* Timing Control 1 */
case 0x20: /* Timing Control 1 */
return s->timing[2];
case 0x24: /* Arbitration Priority Control */
case 0x24: /* Arbitration Priority Control */
return s->priority;
case 0x28: /* LCD Panel Configuration */
case 0x28: /* LCD Panel Configuration */
return s->lcd_config;
case 0x2a: /* LCD Horizontal Display Width */
case 0x2a: /* LCD Horizontal Display Width */
return s->x >> 3;
case 0x2c: /* LCD Horizontal Non-display Period */
case 0x2c: /* LCD Horizontal Non-display Period */
return s->hndp;
case 0x2e: /* LCD Vertical Display Height 0 */
case 0x2e: /* LCD Vertical Display Height 0 */
return s->y & 0xff;
case 0x30: /* LCD Vertical Display Height 1 */
case 0x30: /* LCD Vertical Display Height 1 */
return s->y >> 8;
case 0x32: /* LCD Vertical Non-display Period */
case 0x32: /* LCD Vertical Non-display Period */
return s->vndp;
case 0x34: /* LCD HS Pulse-width */
case 0x34: /* LCD HS Pulse-width */
return s->hsync;
case 0x36: /* LCd HS Pulse Start Position */
case 0x36: /* LCd HS Pulse Start Position */
return s->skipx >> 3;
case 0x38: /* LCD VS Pulse-width */
case 0x38: /* LCD VS Pulse-width */
return s->vsync;
case 0x3a: /* LCD VS Pulse Start Position */
case 0x3a: /* LCD VS Pulse Start Position */
return s->skipy;
case 0x3c: /* PCLK Polarity */
case 0x3c: /* PCLK Polarity */
return s->pclk;
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
return s->hssi_config[0];
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
return s->hssi_config[1];
case 0x42: /* High-speed Serial Interface Tx Mode */
case 0x42: /* High-speed Serial Interface Tx Mode */
return s->hssi_config[2];
case 0x44: /* TV Display Configuration */
case 0x44: /* TV Display Configuration */
return s->tv_config;
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits */
return s->tv_timing[(reg - 0x46) >> 1];
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
return s->vbi;
case 0x50: /* TV Horizontal Start Position */
case 0x50: /* TV Horizontal Start Position */
return s->tv_x;
case 0x52: /* TV Vertical Start Position */
case 0x52: /* TV Vertical Start Position */
return s->tv_y;
case 0x54: /* TV Test Pattern Setting */
case 0x54: /* TV Test Pattern Setting */
return s->tv_test;
case 0x56: /* TV Filter Setting */
case 0x56: /* TV Filter Setting */
return s->tv_filter_config;
case 0x58: /* TV Filter Coefficient Index */
case 0x58: /* TV Filter Coefficient Index */
return s->tv_filter_idx;
case 0x5a: /* TV Filter Coefficient Data */
case 0x5a: /* TV Filter Coefficient Data */
if (s->tv_filter_idx < 0x20)
return s->tv_filter_coeff[s->tv_filter_idx ++];
return 0;
case 0x60: /* Input YUV/RGB Translate Mode 0 */
case 0x60: /* Input YUV/RGB Translate Mode 0 */
return s->yrc[0];
case 0x62: /* Input YUV/RGB Translate Mode 1 */
case 0x62: /* Input YUV/RGB Translate Mode 1 */
return s->yrc[1];
case 0x64: /* U Data Fix */
case 0x64: /* U Data Fix */
return s->u;
case 0x66: /* V Data Fix */
case 0x66: /* V Data Fix */
return s->v;
case 0x68: /* Display Mode */
case 0x68: /* Display Mode */
return s->mode;
case 0x6a: /* Special Effects */
case 0x6a: /* Special Effects */
return s->effect;
case 0x6c: /* Input Window X Start Position 0 */
case 0x6c: /* Input Window X Start Position 0 */
return s->ix[0] & 0xff;
case 0x6e: /* Input Window X Start Position 1 */
case 0x6e: /* Input Window X Start Position 1 */
return s->ix[0] >> 3;
case 0x70: /* Input Window Y Start Position 0 */
case 0x70: /* Input Window Y Start Position 0 */
return s->ix[0] & 0xff;
case 0x72: /* Input Window Y Start Position 1 */
case 0x72: /* Input Window Y Start Position 1 */
return s->ix[0] >> 3;
case 0x74: /* Input Window X End Position 0 */
case 0x74: /* Input Window X End Position 0 */
return s->ix[1] & 0xff;
case 0x76: /* Input Window X End Position 1 */
case 0x76: /* Input Window X End Position 1 */
return s->ix[1] >> 3;
case 0x78: /* Input Window Y End Position 0 */
case 0x78: /* Input Window Y End Position 0 */
return s->ix[1] & 0xff;
case 0x7a: /* Input Window Y End Position 1 */
case 0x7a: /* Input Window Y End Position 1 */
return s->ix[1] >> 3;
case 0x7c: /* Output Window X Start Position 0 */
case 0x7c: /* Output Window X Start Position 0 */
return s->ox[0] & 0xff;
case 0x7e: /* Output Window X Start Position 1 */
case 0x7e: /* Output Window X Start Position 1 */
return s->ox[0] >> 3;
case 0x80: /* Output Window Y Start Position 0 */
case 0x80: /* Output Window Y Start Position 0 */
return s->oy[0] & 0xff;
case 0x82: /* Output Window Y Start Position 1 */
case 0x82: /* Output Window Y Start Position 1 */
return s->oy[0] >> 3;
case 0x84: /* Output Window X End Position 0 */
case 0x84: /* Output Window X End Position 0 */
return s->ox[1] & 0xff;
case 0x86: /* Output Window X End Position 1 */
case 0x86: /* Output Window X End Position 1 */
return s->ox[1] >> 3;
case 0x88: /* Output Window Y End Position 0 */
case 0x88: /* Output Window Y End Position 0 */
return s->oy[1] & 0xff;
case 0x8a: /* Output Window Y End Position 1 */
case 0x8a: /* Output Window Y End Position 1 */
return s->oy[1] >> 3;
case 0x8c: /* Input Data Format */
case 0x8c: /* Input Data Format */
return s->iformat;
case 0x8e: /* Data Source Select */
case 0x8e: /* Data Source Select */
return s->source;
case 0x90: /* Display Memory Data Port */
case 0x90: /* Display Memory Data Port */
return 0;
case 0xa8: /* Border Color 0 */
case 0xa8: /* Border Color 0 */
return s->border_r;
case 0xaa: /* Border Color 1 */
case 0xaa: /* Border Color 1 */
return s->border_g;
case 0xac: /* Border Color 2 */
case 0xac: /* Border Color 2 */
return s->border_b;
case 0xb4: /* Gamma Correction Enable */
case 0xb4: /* Gamma Correction Enable */
return s->gamma_config;
case 0xb6: /* Gamma Correction Table Index */
case 0xb6: /* Gamma Correction Table Index */
return s->gamma_idx;
case 0xb8: /* Gamma Correction Table Data */
case 0xb8: /* Gamma Correction Table Data */
return s->gamma_lut[s->gamma_idx ++];
case 0xba: /* 3x3 Matrix Enable */
case 0xba: /* 3x3 Matrix Enable */
return s->matrix_ena;
case 0xbc ... 0xde: /* Coefficient Registers */
case 0xbc ... 0xde: /* Coefficient Registers */
return s->matrix_coeff[(reg - 0xbc) >> 1];
case 0xe0: /* 3x3 Matrix Red Offset */
case 0xe0: /* 3x3 Matrix Red Offset */
return s->matrix_r;
case 0xe2: /* 3x3 Matrix Green Offset */
case 0xe2: /* 3x3 Matrix Green Offset */
return s->matrix_g;
case 0xe4: /* 3x3 Matrix Blue Offset */
case 0xe4: /* 3x3 Matrix Blue Offset */
return s->matrix_b;
case 0xe6: /* Power-save */
case 0xe6: /* Power-save */
return s->pm;
case 0xe8: /* Non-display Period Control / Status */
case 0xe8: /* Non-display Period Control / Status */
return s->status | (1 << 5);
case 0xea: /* RGB Interface Control */
case 0xea: /* RGB Interface Control */
return s->rgbgpio_dir;
case 0xec: /* RGB Interface Status */
case 0xec: /* RGB Interface Status */
return s->rgbgpio;
case 0xee: /* General-purpose IO Pins Configuration */
case 0xee: /* General-purpose IO Pins Configuration */
return s->gpio_dir;
case 0xf0: /* General-purpose IO Pins Status / Control */
case 0xf0: /* General-purpose IO Pins Status / Control */
return s->gpio;
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
return s->gpio_edge[0];
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
return s->gpio_edge[1];
case 0xf6: /* GPIO Interrupt Status */
case 0xf6: /* GPIO Interrupt Status */
return s->gpio_irq;
case 0xf8: /* GPIO Pull-down Control */
case 0xf8: /* GPIO Pull-down Control */
return s->gpio_pdown;
default:
@ -484,157 +484,157 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
BlizzardState *s = (BlizzardState *) opaque;
switch (reg) {
case 0x04: /* PLL M-Divider */
case 0x04: /* PLL M-Divider */
s->pll = (value & 0x3f) + 1;
break;
case 0x06: /* PLL Lock Range Control */
case 0x06: /* PLL Lock Range Control */
s->pll_range = value & 3;
break;
case 0x08: /* PLL Lock Synthesis Control 0 */
case 0x08: /* PLL Lock Synthesis Control 0 */
s->pll_ctrl &= 0xf00;
s->pll_ctrl |= (value << 0) & 0x0ff;
break;
case 0x0a: /* PLL Lock Synthesis Control 1 */
case 0x0a: /* PLL Lock Synthesis Control 1 */
s->pll_ctrl &= 0x0ff;
s->pll_ctrl |= (value << 8) & 0xf00;
break;
case 0x0c: /* PLL Mode Control 0 */
case 0x0c: /* PLL Mode Control 0 */
s->pll_mode = value & 0x77;
if ((value & 3) == 0 || (value & 3) == 3)
fprintf(stderr, "%s: wrong PLL Control bits (%i)\n",
__func__, value & 3);
break;
case 0x0e: /* Clock-Source Select */
case 0x0e: /* Clock-Source Select */
s->clksel = value & 0xff;
break;
case 0x10: /* Memory Controller Activate */
case 0x10: /* Memory Controller Activate */
s->memenable = value & 1;
break;
case 0x14: /* Memory Controller Bank 0 Status Flag */
case 0x14: /* Memory Controller Bank 0 Status Flag */
break;
case 0x18: /* Auto-Refresh Interval Setting 0 */
case 0x18: /* Auto-Refresh Interval Setting 0 */
s->memrefresh &= 0xf00;
s->memrefresh |= (value << 0) & 0x0ff;
break;
case 0x1a: /* Auto-Refresh Interval Setting 1 */
case 0x1a: /* Auto-Refresh Interval Setting 1 */
s->memrefresh &= 0x0ff;
s->memrefresh |= (value << 8) & 0xf00;
break;
case 0x1c: /* Power-On Sequence Timing Control */
case 0x1c: /* Power-On Sequence Timing Control */
s->timing[0] = value & 0x7f;
break;
case 0x1e: /* Timing Control 0 */
case 0x1e: /* Timing Control 0 */
s->timing[1] = value & 0x17;
break;
case 0x20: /* Timing Control 1 */
case 0x20: /* Timing Control 1 */
s->timing[2] = value & 0x35;
break;
case 0x24: /* Arbitration Priority Control */
case 0x24: /* Arbitration Priority Control */
s->priority = value & 1;
break;
case 0x28: /* LCD Panel Configuration */
case 0x28: /* LCD Panel Configuration */
s->lcd_config = value & 0xff;
if (value & (1 << 7))
fprintf(stderr, "%s: data swap not supported!\n", __func__);
break;
case 0x2a: /* LCD Horizontal Display Width */
case 0x2a: /* LCD Horizontal Display Width */
s->x = value << 3;
break;
case 0x2c: /* LCD Horizontal Non-display Period */
case 0x2c: /* LCD Horizontal Non-display Period */
s->hndp = value & 0xff;
break;
case 0x2e: /* LCD Vertical Display Height 0 */
case 0x2e: /* LCD Vertical Display Height 0 */
s->y &= 0x300;
s->y |= (value << 0) & 0x0ff;
break;
case 0x30: /* LCD Vertical Display Height 1 */
case 0x30: /* LCD Vertical Display Height 1 */
s->y &= 0x0ff;
s->y |= (value << 8) & 0x300;
break;
case 0x32: /* LCD Vertical Non-display Period */
case 0x32: /* LCD Vertical Non-display Period */
s->vndp = value & 0xff;
break;
case 0x34: /* LCD HS Pulse-width */
case 0x34: /* LCD HS Pulse-width */
s->hsync = value & 0xff;
break;
case 0x36: /* LCD HS Pulse Start Position */
case 0x36: /* LCD HS Pulse Start Position */
s->skipx = value & 0xff;
break;
case 0x38: /* LCD VS Pulse-width */
case 0x38: /* LCD VS Pulse-width */
s->vsync = value & 0xbf;
break;
case 0x3a: /* LCD VS Pulse Start Position */
case 0x3a: /* LCD VS Pulse Start Position */
s->skipy = value & 0xff;
break;
case 0x3c: /* PCLK Polarity */
case 0x3c: /* PCLK Polarity */
s->pclk = value & 0x82;
/* Affects calculation of s->hndp, s->hsync and s->skipx. */
break;
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
case 0x3e: /* High-speed Serial Interface Tx Configuration Port 0 */
s->hssi_config[0] = value;
break;
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
case 0x40: /* High-speed Serial Interface Tx Configuration Port 1 */
s->hssi_config[1] = value;
if (((value >> 4) & 3) == 3)
fprintf(stderr, "%s: Illegal active-data-links value\n",
__func__);
break;
case 0x42: /* High-speed Serial Interface Tx Mode */
case 0x42: /* High-speed Serial Interface Tx Mode */
s->hssi_config[2] = value & 0xbd;
break;
case 0x44: /* TV Display Configuration */
case 0x44: /* TV Display Configuration */
s->tv_config = value & 0xfe;
break;
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
case 0x46 ... 0x4c: /* TV Vertical Blanking Interval Data bits 0 */
s->tv_timing[(reg - 0x46) >> 1] = value;
break;
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
case 0x4e: /* VBI: Closed Caption / XDS Control / Status */
s->vbi = value;
break;
case 0x50: /* TV Horizontal Start Position */
case 0x50: /* TV Horizontal Start Position */
s->tv_x = value;
break;
case 0x52: /* TV Vertical Start Position */
case 0x52: /* TV Vertical Start Position */
s->tv_y = value & 0x7f;
break;
case 0x54: /* TV Test Pattern Setting */
case 0x54: /* TV Test Pattern Setting */
s->tv_test = value;
break;
case 0x56: /* TV Filter Setting */
case 0x56: /* TV Filter Setting */
s->tv_filter_config = value & 0xbf;
break;
case 0x58: /* TV Filter Coefficient Index */
case 0x58: /* TV Filter Coefficient Index */
s->tv_filter_idx = value & 0x1f;
break;
case 0x5a: /* TV Filter Coefficient Data */
case 0x5a: /* TV Filter Coefficient Data */
if (s->tv_filter_idx < 0x20)
s->tv_filter_coeff[s->tv_filter_idx ++] = value;
break;
case 0x60: /* Input YUV/RGB Translate Mode 0 */
case 0x60: /* Input YUV/RGB Translate Mode 0 */
s->yrc[0] = value & 0xb0;
break;
case 0x62: /* Input YUV/RGB Translate Mode 1 */
case 0x62: /* Input YUV/RGB Translate Mode 1 */
s->yrc[1] = value & 0x30;
break;
case 0x64: /* U Data Fix */
case 0x64: /* U Data Fix */
s->u = value & 0xff;
break;
case 0x66: /* V Data Fix */
case 0x66: /* V Data Fix */
s->v = value & 0xff;
break;
case 0x68: /* Display Mode */
case 0x68: /* Display Mode */
if ((s->mode ^ value) & 3)
s->invalidate = 1;
s->mode = value & 0xb7;
@ -644,83 +644,83 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
fprintf(stderr, "%s: Macrovision enable attempt!\n", __func__);
break;
case 0x6a: /* Special Effects */
case 0x6a: /* Special Effects */
s->effect = value & 0xfb;
break;
case 0x6c: /* Input Window X Start Position 0 */
case 0x6c: /* Input Window X Start Position 0 */
s->ix[0] &= 0x300;
s->ix[0] |= (value << 0) & 0x0ff;
break;
case 0x6e: /* Input Window X Start Position 1 */
case 0x6e: /* Input Window X Start Position 1 */
s->ix[0] &= 0x0ff;
s->ix[0] |= (value << 8) & 0x300;
break;
case 0x70: /* Input Window Y Start Position 0 */
case 0x70: /* Input Window Y Start Position 0 */
s->iy[0] &= 0x300;
s->iy[0] |= (value << 0) & 0x0ff;
break;
case 0x72: /* Input Window Y Start Position 1 */
case 0x72: /* Input Window Y Start Position 1 */
s->iy[0] &= 0x0ff;
s->iy[0] |= (value << 8) & 0x300;
break;
case 0x74: /* Input Window X End Position 0 */
case 0x74: /* Input Window X End Position 0 */
s->ix[1] &= 0x300;
s->ix[1] |= (value << 0) & 0x0ff;
break;
case 0x76: /* Input Window X End Position 1 */
case 0x76: /* Input Window X End Position 1 */
s->ix[1] &= 0x0ff;
s->ix[1] |= (value << 8) & 0x300;
break;
case 0x78: /* Input Window Y End Position 0 */
case 0x78: /* Input Window Y End Position 0 */
s->iy[1] &= 0x300;
s->iy[1] |= (value << 0) & 0x0ff;
break;
case 0x7a: /* Input Window Y End Position 1 */
case 0x7a: /* Input Window Y End Position 1 */
s->iy[1] &= 0x0ff;
s->iy[1] |= (value << 8) & 0x300;
break;
case 0x7c: /* Output Window X Start Position 0 */
case 0x7c: /* Output Window X Start Position 0 */
s->ox[0] &= 0x300;
s->ox[0] |= (value << 0) & 0x0ff;
break;
case 0x7e: /* Output Window X Start Position 1 */
case 0x7e: /* Output Window X Start Position 1 */
s->ox[0] &= 0x0ff;
s->ox[0] |= (value << 8) & 0x300;
break;
case 0x80: /* Output Window Y Start Position 0 */
case 0x80: /* Output Window Y Start Position 0 */
s->oy[0] &= 0x300;
s->oy[0] |= (value << 0) & 0x0ff;
break;
case 0x82: /* Output Window Y Start Position 1 */
case 0x82: /* Output Window Y Start Position 1 */
s->oy[0] &= 0x0ff;
s->oy[0] |= (value << 8) & 0x300;
break;
case 0x84: /* Output Window X End Position 0 */
case 0x84: /* Output Window X End Position 0 */
s->ox[1] &= 0x300;
s->ox[1] |= (value << 0) & 0x0ff;
break;
case 0x86: /* Output Window X End Position 1 */
case 0x86: /* Output Window X End Position 1 */
s->ox[1] &= 0x0ff;
s->ox[1] |= (value << 8) & 0x300;
break;
case 0x88: /* Output Window Y End Position 0 */
case 0x88: /* Output Window Y End Position 0 */
s->oy[1] &= 0x300;
s->oy[1] |= (value << 0) & 0x0ff;
break;
case 0x8a: /* Output Window Y End Position 1 */
case 0x8a: /* Output Window Y End Position 1 */
s->oy[1] &= 0x0ff;
s->oy[1] |= (value << 8) & 0x300;
break;
case 0x8c: /* Input Data Format */
case 0x8c: /* Input Data Format */
s->iformat = value & 0xf;
s->bpp = blizzard_iformat_bpp[s->iformat];
if (!s->bpp)
fprintf(stderr, "%s: Illegal or unsupported input format %x\n",
__func__, s->iformat);
break;
case 0x8e: /* Data Source Select */
case 0x8e: /* Data Source Select */
s->source = value & 7;
/* Currently all windows will be "destructive overlays". */
if ((!(s->effect & (1 << 3)) && (s->ix[0] != s->ox[0] ||
@ -735,7 +735,7 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
blizzard_transfer_setup(s);
break;
case 0x90: /* Display Memory Data Port */
case 0x90: /* Display Memory Data Port */
if (!s->data.len && !blizzard_transfer_setup(s))
break;
@ -744,73 +744,73 @@ static void blizzard_reg_write(void *opaque, uint8_t reg, uint16_t value)
blizzard_window(s);
break;
case 0xa8: /* Border Color 0 */
case 0xa8: /* Border Color 0 */
s->border_r = value;
break;
case 0xaa: /* Border Color 1 */
case 0xaa: /* Border Color 1 */
s->border_g = value;
break;
case 0xac: /* Border Color 2 */
case 0xac: /* Border Color 2 */
s->border_b = value;
break;
case 0xb4: /* Gamma Correction Enable */
case 0xb4: /* Gamma Correction Enable */
s->gamma_config = value & 0x87;
break;
case 0xb6: /* Gamma Correction Table Index */
case 0xb6: /* Gamma Correction Table Index */
s->gamma_idx = value;
break;
case 0xb8: /* Gamma Correction Table Data */
case 0xb8: /* Gamma Correction Table Data */
s->gamma_lut[s->gamma_idx ++] = value;
break;
case 0xba: /* 3x3 Matrix Enable */
case 0xba: /* 3x3 Matrix Enable */
s->matrix_ena = value & 1;
break;
case 0xbc ... 0xde: /* Coefficient Registers */
case 0xbc ... 0xde: /* Coefficient Registers */
s->matrix_coeff[(reg - 0xbc) >> 1] = value & ((reg & 2) ? 0x80 : 0xff);
break;
case 0xe0: /* 3x3 Matrix Red Offset */
case 0xe0: /* 3x3 Matrix Red Offset */
s->matrix_r = value;
break;
case 0xe2: /* 3x3 Matrix Green Offset */
case 0xe2: /* 3x3 Matrix Green Offset */
s->matrix_g = value;
break;
case 0xe4: /* 3x3 Matrix Blue Offset */
case 0xe4: /* 3x3 Matrix Blue Offset */
s->matrix_b = value;
break;
case 0xe6: /* Power-save */
case 0xe6: /* Power-save */
s->pm = value & 0x83;
if (value & s->mode & 1)
fprintf(stderr, "%s: The display must be disabled before entering "
"Standby Mode\n", __func__);
break;
case 0xe8: /* Non-display Period Control / Status */
case 0xe8: /* Non-display Period Control / Status */
s->status = value & 0x1b;
break;
case 0xea: /* RGB Interface Control */
case 0xea: /* RGB Interface Control */
s->rgbgpio_dir = value & 0x8f;
break;
case 0xec: /* RGB Interface Status */
case 0xec: /* RGB Interface Status */
s->rgbgpio = value & 0xcf;
break;
case 0xee: /* General-purpose IO Pins Configuration */
case 0xee: /* General-purpose IO Pins Configuration */
s->gpio_dir = value;
break;
case 0xf0: /* General-purpose IO Pins Status / Control */
case 0xf0: /* General-purpose IO Pins Status / Control */
s->gpio = value;
break;
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
case 0xf2: /* GPIO Positive Edge Interrupt Trigger */
s->gpio_edge[0] = value;
break;
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
case 0xf4: /* GPIO Negative Edge Interrupt Trigger */
s->gpio_edge[1] = value;
break;
case 0xf6: /* GPIO Interrupt Status */
case 0xf6: /* GPIO Interrupt Status */
s->gpio_irq &= value;
break;
case 0xf8: /* GPIO Pull-down Control */
case 0xf8: /* GPIO Pull-down Control */
s->gpio_pdown = value;
break;

1600
hw/display/cirrus_vga.c
View File

File diff suppressed because it is too large Load Diff

598
hw/display/omap_dss.c
View File

@ -182,25 +182,25 @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
case 0x00: /* DSS_REVISIONNUMBER */
return 0x20;
case 0x10: /* DSS_SYSCONFIG */
case 0x10: /* DSS_SYSCONFIG */
return s->autoidle;
case 0x14: /* DSS_SYSSTATUS */
return 1; /* RESETDONE */
case 0x14: /* DSS_SYSSTATUS */
return 1; /* RESETDONE */
case 0x40: /* DSS_CONTROL */
case 0x40: /* DSS_CONTROL */
return s->control;
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
/* TODO: fake some values when appropriate s->control bits are set */
return 0;
case 0x5c: /* DSS_STATUS */
case 0x5c: /* DSS_STATUS */
return 1 + (s->control & 1);
default:
@ -221,22 +221,22 @@ static void omap_diss_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* DSS_REVISIONNUMBER */
case 0x14: /* DSS_SYSSTATUS */
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
case 0x5c: /* DSS_STATUS */
case 0x00: /* DSS_REVISIONNUMBER */
case 0x14: /* DSS_SYSSTATUS */
case 0x50: /* DSS_PSA_LCD_REG_1 */
case 0x54: /* DSS_PSA_LCD_REG_2 */
case 0x58: /* DSS_PSA_VIDEO_REG */
case 0x5c: /* DSS_STATUS */
OMAP_RO_REG(addr);
break;
case 0x10: /* DSS_SYSCONFIG */
if (value & 2) /* SOFTRESET */
case 0x10: /* DSS_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dss_reset(s);
s->autoidle = value & 1;
break;
case 0x40: /* DSS_CONTROL */
case 0x40: /* DSS_CONTROL */
s->control = value & 0x3dd;
break;
@ -261,112 +261,112 @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x000: /* DISPC_REVISION */
case 0x000: /* DISPC_REVISION */
return 0x20;
case 0x010: /* DISPC_SYSCONFIG */
case 0x010: /* DISPC_SYSCONFIG */
return s->dispc.idlemode;
case 0x014: /* DISPC_SYSSTATUS */
return 1; /* RESETDONE */
case 0x014: /* DISPC_SYSSTATUS */
return 1; /* RESETDONE */
case 0x018: /* DISPC_IRQSTATUS */
case 0x018: /* DISPC_IRQSTATUS */
return s->dispc.irqst;
case 0x01c: /* DISPC_IRQENABLE */
case 0x01c: /* DISPC_IRQENABLE */
return s->dispc.irqen;
case 0x040: /* DISPC_CONTROL */
case 0x040: /* DISPC_CONTROL */
return s->dispc.control;
case 0x044: /* DISPC_CONFIG */
case 0x044: /* DISPC_CONFIG */
return s->dispc.config;
case 0x048: /* DISPC_CAPABLE */
case 0x048: /* DISPC_CAPABLE */
return s->dispc.capable;
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
return s->dispc.bg[0];
case 0x050: /* DISPC_DEFAULT_COLOR1 */
case 0x050: /* DISPC_DEFAULT_COLOR1 */
return s->dispc.bg[1];
case 0x054: /* DISPC_TRANS_COLOR0 */
case 0x054: /* DISPC_TRANS_COLOR0 */
return s->dispc.trans[0];
case 0x058: /* DISPC_TRANS_COLOR1 */
case 0x058: /* DISPC_TRANS_COLOR1 */
return s->dispc.trans[1];
case 0x05c: /* DISPC_LINE_STATUS */
case 0x05c: /* DISPC_LINE_STATUS */
return 0x7ff;
case 0x060: /* DISPC_LINE_NUMBER */
case 0x060: /* DISPC_LINE_NUMBER */
return s->dispc.line;
case 0x064: /* DISPC_TIMING_H */
case 0x064: /* DISPC_TIMING_H */
return s->dispc.timing[0];
case 0x068: /* DISPC_TIMING_V */
case 0x068: /* DISPC_TIMING_V */
return s->dispc.timing[1];
case 0x06c: /* DISPC_POL_FREQ */
case 0x06c: /* DISPC_POL_FREQ */
return s->dispc.timing[2];
case 0x070: /* DISPC_DIVISOR */
case 0x070: /* DISPC_DIVISOR */
return s->dispc.timing[3];
case 0x078: /* DISPC_SIZE_DIG */
case 0x078: /* DISPC_SIZE_DIG */
return ((s->dig.ny - 1) << 16) | (s->dig.nx - 1);
case 0x07c: /* DISPC_SIZE_LCD */
case 0x07c: /* DISPC_SIZE_LCD */
return ((s->lcd.ny - 1) << 16) | (s->lcd.nx - 1);
case 0x080: /* DISPC_GFX_BA0 */
case 0x080: /* DISPC_GFX_BA0 */
return s->dispc.l[0].addr[0];
case 0x084: /* DISPC_GFX_BA1 */
case 0x084: /* DISPC_GFX_BA1 */
return s->dispc.l[0].addr[1];
case 0x088: /* DISPC_GFX_POSITION */
case 0x088: /* DISPC_GFX_POSITION */
return (s->dispc.l[0].posy << 16) | s->dispc.l[0].posx;
case 0x08c: /* DISPC_GFX_SIZE */
case 0x08c: /* DISPC_GFX_SIZE */
return ((s->dispc.l[0].ny - 1) << 16) | (s->dispc.l[0].nx - 1);
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
return s->dispc.l[0].attr;
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
return s->dispc.l[0].tresh;
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
case 0x0a8: /* DISPC_GFX_FIFO_SIZE_STATUS */
return 256;
case 0x0ac: /* DISPC_GFX_ROW_INC */
case 0x0ac: /* DISPC_GFX_ROW_INC */
return s->dispc.l[0].rowinc;
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
return s->dispc.l[0].colinc;
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
return s->dispc.l[0].wininc;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
case 0x0b8: /* DISPC_GFX_TABLE_BA */
return s->dispc.l[0].addr[2];
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d4: /* DISPC_VID1_FIFO_SIZE_STATUS */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x164: /* DISPC_VID2_FIFO_SIZE_STATUS */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
return 0;
default:
@ -387,33 +387,33 @@ static void omap_disc_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x010: /* DISPC_SYSCONFIG */
if (value & 2) /* SOFTRESET */
case 0x010: /* DISPC_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_dss_reset(s);
s->dispc.idlemode = value & 0x301b;
break;
case 0x018: /* DISPC_IRQSTATUS */
case 0x018: /* DISPC_IRQSTATUS */
s->dispc.irqst &= ~value;
omap_dispc_interrupt_update(s);
break;
case 0x01c: /* DISPC_IRQENABLE */
case 0x01c: /* DISPC_IRQENABLE */
s->dispc.irqen = value & 0xffff;
omap_dispc_interrupt_update(s);
break;
case 0x040: /* DISPC_CONTROL */
case 0x040: /* DISPC_CONTROL */
s->dispc.control = value & 0x07ff9fff;
s->dig.enable = (value >> 1) & 1;
s->lcd.enable = (value >> 0) & 1;
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
if (value & (1 << 12)) /* OVERLAY_OPTIMIZATION */
if (!((s->dispc.l[1].attr | s->dispc.l[2].attr) & 1)) {
fprintf(stderr, "%s: Overlay Optimization when no overlay "
"region effectively exists leads to "
"unpredictable behaviour!\n", __func__);
}
if (value & (1 << 6)) { /* GODIGITAL */
if (value & (1 << 6)) { /* GODIGITAL */
/* XXX: Shadowed fields are:
* s->dispc.config
* s->dispc.capable
@ -444,13 +444,13 @@ static void omap_disc_write(void *opaque, hwaddr addr,
* All they need to be loaded here from their shadow registers.
*/
}
if (value & (1 << 5)) { /* GOLCD */
if (value & (1 << 5)) { /* GOLCD */
/* XXX: Likewise for LCD here. */
}
s->dispc.invalidate = 1;
break;
case 0x044: /* DISPC_CONFIG */
case 0x044: /* DISPC_CONFIG */
s->dispc.config = value & 0x3fff;
/* XXX:
* bits 2:1 (LOADMODE) reset to 0 after set to 1 and palette loaded
@ -459,73 +459,73 @@ static void omap_disc_write(void *opaque, hwaddr addr,
s->dispc.invalidate = 1;
break;
case 0x048: /* DISPC_CAPABLE */
case 0x048: /* DISPC_CAPABLE */
s->dispc.capable = value & 0x3ff;
break;
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
case 0x04c: /* DISPC_DEFAULT_COLOR0 */
s->dispc.bg[0] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x050: /* DISPC_DEFAULT_COLOR1 */
case 0x050: /* DISPC_DEFAULT_COLOR1 */
s->dispc.bg[1] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x054: /* DISPC_TRANS_COLOR0 */
case 0x054: /* DISPC_TRANS_COLOR0 */
s->dispc.trans[0] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x058: /* DISPC_TRANS_COLOR1 */
case 0x058: /* DISPC_TRANS_COLOR1 */
s->dispc.trans[1] = value & 0xffffff;
s->dispc.invalidate = 1;
break;
case 0x060: /* DISPC_LINE_NUMBER */
case 0x060: /* DISPC_LINE_NUMBER */
s->dispc.line = value & 0x7ff;
break;
case 0x064: /* DISPC_TIMING_H */
case 0x064: /* DISPC_TIMING_H */
s->dispc.timing[0] = value & 0x0ff0ff3f;
break;
case 0x068: /* DISPC_TIMING_V */
case 0x068: /* DISPC_TIMING_V */
s->dispc.timing[1] = value & 0x0ff0ff3f;
break;
case 0x06c: /* DISPC_POL_FREQ */
case 0x06c: /* DISPC_POL_FREQ */
s->dispc.timing[2] = value & 0x0003ffff;
break;
case 0x070: /* DISPC_DIVISOR */
case 0x070: /* DISPC_DIVISOR */
s->dispc.timing[3] = value & 0x00ff00ff;
break;
case 0x078: /* DISPC_SIZE_DIG */
s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
case 0x078: /* DISPC_SIZE_DIG */
s->dig.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->dig.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
s->dispc.invalidate = 1;
break;
case 0x07c: /* DISPC_SIZE_LCD */
s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
case 0x07c: /* DISPC_SIZE_LCD */
s->lcd.nx = ((value >> 0) & 0x7ff) + 1; /* PPL */
s->lcd.ny = ((value >> 16) & 0x7ff) + 1; /* LPP */
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
case 0x080: /* DISPC_GFX_BA0 */
s->dispc.l[0].addr[0] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
case 0x084: /* DISPC_GFX_BA1 */
s->dispc.l[0].addr[1] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
case 0x088: /* DISPC_GFX_POSITION */
s->dispc.l[0].posx = ((value >> 0) & 0x7ff); /* GFXPOSX */
s->dispc.l[0].posy = ((value >> 16) & 0x7ff); /* GFXPOSY */
s->dispc.invalidate = 1;
break;
case 0x08c: /* DISPC_GFX_SIZE */
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
case 0x08c: /* DISPC_GFX_SIZE */
s->dispc.l[0].nx = ((value >> 0) & 0x7ff) + 1; /* GFXSIZEX */
s->dispc.l[0].ny = ((value >> 16) & 0x7ff) + 1; /* GFXSIZEY */
s->dispc.invalidate = 1;
break;
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
case 0x0a0: /* DISPC_GFX_ATTRIBUTES */
s->dispc.l[0].attr = value & 0x7ff;
if (value & (3 << 9))
fprintf(stderr, "%s: Big-endian pixel format not supported\n",
@ -534,54 +534,54 @@ static void omap_disc_write(void *opaque, hwaddr addr,
s->dispc.l[0].bpp = (value >> 1) & 0xf;
s->dispc.invalidate = 1;
break;
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
case 0x0a4: /* DISPC_GFX_FIFO_TRESHOLD */
s->dispc.l[0].tresh = value & 0x01ff01ff;
break;
case 0x0ac: /* DISPC_GFX_ROW_INC */
case 0x0ac: /* DISPC_GFX_ROW_INC */
s->dispc.l[0].rowinc = value;
s->dispc.invalidate = 1;
break;
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
case 0x0b0: /* DISPC_GFX_PIXEL_INC */
s->dispc.l[0].colinc = value;
s->dispc.invalidate = 1;
break;
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
case 0x0b4: /* DISPC_GFX_WINDOW_SKIP */
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
case 0x0b8: /* DISPC_GFX_TABLE_BA */
s->dispc.l[0].addr[2] = (hwaddr) value;
s->dispc.invalidate = 1;
break;
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
case 0x0bc: /* DISPC_VID1_BA0 */
case 0x0c0: /* DISPC_VID1_BA1 */
case 0x0c4: /* DISPC_VID1_POSITION */
case 0x0c8: /* DISPC_VID1_SIZE */
case 0x0cc: /* DISPC_VID1_ATTRIBUTES */
case 0x0d0: /* DISPC_VID1_FIFO_TRESHOLD */
case 0x0d8: /* DISPC_VID1_ROW_INC */
case 0x0dc: /* DISPC_VID1_PIXEL_INC */
case 0x0e0: /* DISPC_VID1_FIR */
case 0x0e4: /* DISPC_VID1_PICTURE_SIZE */
case 0x0e8: /* DISPC_VID1_ACCU0 */
case 0x0ec: /* DISPC_VID1_ACCU1 */
case 0x0f0 ... 0x140: /* DISPC_VID1_FIR_COEF, DISPC_VID1_CONV_COEF */
case 0x14c: /* DISPC_VID2_BA0 */
case 0x150: /* DISPC_VID2_BA1 */
case 0x154: /* DISPC_VID2_POSITION */
case 0x158: /* DISPC_VID2_SIZE */
case 0x15c: /* DISPC_VID2_ATTRIBUTES */
case 0x160: /* DISPC_VID2_FIFO_TRESHOLD */
case 0x168: /* DISPC_VID2_ROW_INC */
case 0x16c: /* DISPC_VID2_PIXEL_INC */
case 0x170: /* DISPC_VID2_FIR */
case 0x174: /* DISPC_VID2_PICTURE_SIZE */
case 0x178: /* DISPC_VID2_ACCU0 */
case 0x17c: /* DISPC_VID2_ACCU1 */
case 0x180 ... 0x1d0: /* DISPC_VID2_FIR_COEF, DISPC_VID2_CONV_COEF */
case 0x1d4: /* DISPC_DATA_CYCLE1 */
case 0x1d8: /* DISPC_DATA_CYCLE2 */
case 0x1dc: /* DISPC_DATA_CYCLE3 */
break;
default:
@ -617,14 +617,14 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
if (!s->rfbi.enable || s->rfbi.busy)
return;
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
if (s->rfbi.control & (1 << 1)) { /* BYPASS */
/* TODO: in non-Bypass mode we probably need to just assert the
* DRQ and wait for DMA to write the pixels. */
qemu_log_mask(LOG_UNIMP, "%s: Bypass mode unimplemented\n", __func__);
return;
}
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
if (!(s->dispc.control & (1 << 11))) /* RFBIMODE */
return;
/* TODO: check that LCD output is enabled in DISPC. */
@ -665,7 +665,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_rfbi_transfer_stop(s);
/* TODO */
s->dispc.irqst |= 1; /* FRAMEDONE */
s->dispc.irqst |= 1; /* FRAMEDONE */
omap_dispc_interrupt_update(s);
}
@ -679,57 +679,57 @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* RFBI_REVISION */
case 0x00: /* RFBI_REVISION */
return 0x10;
case 0x10: /* RFBI_SYSCONFIG */
case 0x10: /* RFBI_SYSCONFIG */
return s->rfbi.idlemode;
case 0x14: /* RFBI_SYSSTATUS */
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
case 0x14: /* RFBI_SYSSTATUS */
return 1 | (s->rfbi.busy << 8); /* RESETDONE */
case 0x40: /* RFBI_CONTROL */
case 0x40: /* RFBI_CONTROL */
return s->rfbi.control;
case 0x44: /* RFBI_PIXELCNT */
case 0x44: /* RFBI_PIXELCNT */
return s->rfbi.pixels;
case 0x48: /* RFBI_LINE_NUMBER */
case 0x48: /* RFBI_LINE_NUMBER */
return s->rfbi.skiplines;
case 0x58: /* RFBI_READ */
case 0x5c: /* RFBI_STATUS */
case 0x58: /* RFBI_READ */
case 0x5c: /* RFBI_STATUS */
return s->rfbi.rxbuf;
case 0x60: /* RFBI_CONFIG0 */
case 0x60: /* RFBI_CONFIG0 */
return s->rfbi.config[0];
case 0x64: /* RFBI_ONOFF_TIME0 */
case 0x64: /* RFBI_ONOFF_TIME0 */
return s->rfbi.time[0];
case 0x68: /* RFBI_CYCLE_TIME0 */
case 0x68: /* RFBI_CYCLE_TIME0 */
return s->rfbi.time[1];
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
return s->rfbi.data[0];
case 0x70: /* RFBI_DATA_CYCLE2_0 */
case 0x70: /* RFBI_DATA_CYCLE2_0 */
return s->rfbi.data[1];
case 0x74: /* RFBI_DATA_CYCLE3_0 */
case 0x74: /* RFBI_DATA_CYCLE3_0 */
return s->rfbi.data[2];
case 0x78: /* RFBI_CONFIG1 */
case 0x78: /* RFBI_CONFIG1 */
return s->rfbi.config[1];
case 0x7c: /* RFBI_ONOFF_TIME1 */
case 0x7c: /* RFBI_ONOFF_TIME1 */
return s->rfbi.time[2];
case 0x80: /* RFBI_CYCLE_TIME1 */
case 0x80: /* RFBI_CYCLE_TIME1 */
return s->rfbi.time[3];
case 0x84: /* RFBI_DATA_CYCLE1_1 */
case 0x84: /* RFBI_DATA_CYCLE1_1 */
return s->rfbi.data[3];
case 0x88: /* RFBI_DATA_CYCLE2_1 */
case 0x88: /* RFBI_DATA_CYCLE2_1 */
return s->rfbi.data[4];
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
return s->rfbi.data[5];
case 0x90: /* RFBI_VSYNC_WIDTH */
case 0x90: /* RFBI_VSYNC_WIDTH */
return s->rfbi.vsync;
case 0x94: /* RFBI_HSYNC_WIDTH */
case 0x94: /* RFBI_HSYNC_WIDTH */
return s->rfbi.hsync;
}
OMAP_BAD_REG(addr);
@ -747,41 +747,41 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x10: /* RFBI_SYSCONFIG */
if (value & 2) /* SOFTRESET */
case 0x10: /* RFBI_SYSCONFIG */
if (value & 2) /* SOFTRESET */
omap_rfbi_reset(s);
s->rfbi.idlemode = value & 0x19;
break;
case 0x40: /* RFBI_CONTROL */
case 0x40: /* RFBI_CONTROL */
s->rfbi.control = value & 0xf;
s->rfbi.enable = value & 1;
if (value & (1 << 4) && /* ITE */
if (value & (1 << 4) && /* ITE */
!(s->rfbi.config[0] & s->rfbi.config[1] & 0xc))
omap_rfbi_transfer_start(s);
break;
case 0x44: /* RFBI_PIXELCNT */
case 0x44: /* RFBI_PIXELCNT */
s->rfbi.pixels = value;
break;
case 0x48: /* RFBI_LINE_NUMBER */
case 0x48: /* RFBI_LINE_NUMBER */
s->rfbi.skiplines = value & 0x7ff;
break;
case 0x4c: /* RFBI_CMD */
case 0x4c: /* RFBI_CMD */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 0, value & 0xffff);
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 0, value & 0xffff);
break;
case 0x50: /* RFBI_PARAM */
case 0x50: /* RFBI_PARAM */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.chip[0]->write(s->rfbi.chip[0]->opaque, 1, value & 0xffff);
if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
s->rfbi.chip[1]->write(s->rfbi.chip[1]->opaque, 1, value & 0xffff);
break;
case 0x54: /* RFBI_DATA */
case 0x54: /* RFBI_DATA */
/* TODO: take into account the format set up in s->rfbi.config[?] and
* s->rfbi.data[?], but special-case the most usual scenario so that
* speed doesn't suffer. */
@ -796,7 +796,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
if (!-- s->rfbi.pixels)
omap_rfbi_transfer_stop(s);
break;
case 0x58: /* RFBI_READ */
case 0x58: /* RFBI_READ */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 1);
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
@ -805,7 +805,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
omap_rfbi_transfer_stop(s);
break;
case 0x5c: /* RFBI_STATUS */
case 0x5c: /* RFBI_STATUS */
if ((s->rfbi.control & (1 << 2)) && s->rfbi.chip[0])
s->rfbi.rxbuf = s->rfbi.chip[0]->read(s->rfbi.chip[0]->opaque, 0);
else if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1])
@ -814,49 +814,49 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
omap_rfbi_transfer_stop(s);
break;
case 0x60: /* RFBI_CONFIG0 */
case 0x60: /* RFBI_CONFIG0 */
s->rfbi.config[0] = value & 0x003f1fff;
break;
case 0x64: /* RFBI_ONOFF_TIME0 */
case 0x64: /* RFBI_ONOFF_TIME0 */
s->rfbi.time[0] = value & 0x3fffffff;
break;
case 0x68: /* RFBI_CYCLE_TIME0 */
case 0x68: /* RFBI_CYCLE_TIME0 */
s->rfbi.time[1] = value & 0x0fffffff;
break;
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
case 0x6c: /* RFBI_DATA_CYCLE1_0 */
s->rfbi.data[0] = value & 0x0f1f0f1f;
break;
case 0x70: /* RFBI_DATA_CYCLE2_0 */
case 0x70: /* RFBI_DATA_CYCLE2_0 */
s->rfbi.data[1] = value & 0x0f1f0f1f;
break;
case 0x74: /* RFBI_DATA_CYCLE3_0 */
case 0x74: /* RFBI_DATA_CYCLE3_0 */
s->rfbi.data[2] = value & 0x0f1f0f1f;
break;
case 0x78: /* RFBI_CONFIG1 */
case 0x78: /* RFBI_CONFIG1 */
s->rfbi.config[1] = value & 0x003f1fff;
break;
case 0x7c: /* RFBI_ONOFF_TIME1 */
case 0x7c: /* RFBI_ONOFF_TIME1 */
s->rfbi.time[2] = value & 0x3fffffff;
break;
case 0x80: /* RFBI_CYCLE_TIME1 */
case 0x80: /* RFBI_CYCLE_TIME1 */
s->rfbi.time[3] = value & 0x0fffffff;
break;
case 0x84: /* RFBI_DATA_CYCLE1_1 */
case 0x84: /* RFBI_DATA_CYCLE1_1 */
s->rfbi.data[3] = value & 0x0f1f0f1f;
break;
case 0x88: /* RFBI_DATA_CYCLE2_1 */
case 0x88: /* RFBI_DATA_CYCLE2_1 */
s->rfbi.data[4] = value & 0x0f1f0f1f;
break;
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
case 0x8c: /* RFBI_DATA_CYCLE3_1 */
s->rfbi.data[5] = value & 0x0f1f0f1f;
break;
case 0x90: /* RFBI_VSYNC_WIDTH */
case 0x90: /* RFBI_VSYNC_WIDTH */
s->rfbi.vsync = value & 0xffff;
break;
case 0x94: /* RFBI_HSYNC_WIDTH */
case 0x94: /* RFBI_HSYNC_WIDTH */
s->rfbi.hsync = value & 0xffff;
break;
@ -879,49 +879,49 @@ static uint64_t omap_venc_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x00: /* REV_ID */
case 0x04: /* STATUS */
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
case 0x00: /* REV_ID */
case 0x04: /* STATUS */
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
return 0;
default:
@ -940,47 +940,47 @@ static void omap_venc_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
case 0x08: /* F_CONTROL */
case 0x10: /* VIDOUT_CTRL */
case 0x14: /* SYNC_CTRL */
case 0x1c: /* LLEN */
case 0x20: /* FLENS */
case 0x24: /* HFLTR_CTRL */
case 0x28: /* CC_CARR_WSS_CARR */
case 0x2c: /* C_PHASE */
case 0x30: /* GAIN_U */
case 0x34: /* GAIN_V */
case 0x38: /* GAIN_Y */
case 0x3c: /* BLACK_LEVEL */
case 0x40: /* BLANK_LEVEL */
case 0x44: /* X_COLOR */
case 0x48: /* M_CONTROL */
case 0x4c: /* BSTAMP_WSS_DATA */
case 0x50: /* S_CARR */
case 0x54: /* LINE21 */
case 0x58: /* LN_SEL */
case 0x5c: /* L21__WC_CTL */
case 0x60: /* HTRIGGER_VTRIGGER */
case 0x64: /* SAVID__EAVID */
case 0x68: /* FLEN__FAL */
case 0x6c: /* LAL__PHASE_RESET */
case 0x70: /* HS_INT_START_STOP_X */
case 0x74: /* HS_EXT_START_STOP_X */
case 0x78: /* VS_INT_START_X */
case 0x7c: /* VS_INT_STOP_X__VS_INT_START_Y */
case 0x80: /* VS_INT_STOP_Y__VS_INT_START_X */
case 0x84: /* VS_EXT_STOP_X__VS_EXT_START_Y */
case 0x88: /* VS_EXT_STOP_Y */
case 0x90: /* AVID_START_STOP_X */
case 0x94: /* AVID_START_STOP_Y */
case 0xa0: /* FID_INT_START_X__FID_INT_START_Y */
case 0xa4: /* FID_INT_OFFSET_Y__FID_EXT_START_X */
case 0xa8: /* FID_EXT_START_Y__FID_EXT_OFFSET_Y */
case 0xb0: /* TVDETGP_INT_START_STOP_X */
case 0xb4: /* TVDETGP_INT_START_STOP_Y */
case 0xb8: /* GEN_CTRL */
case 0xc4: /* DAC_TST__DAC_A */
case 0xc8: /* DAC_B__DAC_C */
break;
default:
@ -1002,15 +1002,15 @@ static uint64_t omap_im3_read(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x0a8: /* SBIMERRLOGA */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
case 0x1f8: /* SBID_L */
case 0x1fc: /* SBID_H */
case 0x0a8: /* SBIMERRLOGA */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
case 0x1f8: /* SBID_L */
case 0x1fc: /* SBID_H */
return 0;
default:
@ -1029,12 +1029,12 @@ static void omap_im3_write(void *opaque, hwaddr addr,
}
switch (addr) {
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
case 0x0b0: /* SBIMERRLOG */
case 0x190: /* SBIMSTATE */
case 0x198: /* SBTMSTATE_L */
case 0x19c: /* SBTMSTATE_H */
case 0x1a8: /* SBIMCONFIG_L */
case 0x1ac: /* SBIMCONFIG_H */
break;
default:

184
hw/display/pxa2xx_lcd.c
View File

@ -86,106 +86,106 @@ typedef struct QEMU_PACKED {
uint32_t ldcmd;
} PXAFrameDescriptor;
#define LCCR0 0x000 /* LCD Controller Control register 0 */
#define LCCR1 0x004 /* LCD Controller Control register 1 */
#define LCCR2 0x008 /* LCD Controller Control register 2 */
#define LCCR3 0x00c /* LCD Controller Control register 3 */
#define LCCR4 0x010 /* LCD Controller Control register 4 */
#define LCCR5 0x014 /* LCD Controller Control register 5 */
#define LCCR0 0x000 /* LCD Controller Control register 0 */
#define LCCR1 0x004 /* LCD Controller Control register 1 */
#define LCCR2 0x008 /* LCD Controller Control register 2 */
#define LCCR3 0x00c /* LCD Controller Control register 3 */
#define LCCR4 0x010 /* LCD Controller Control register 4 */
#define LCCR5 0x014 /* LCD Controller Control register 5 */
#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
#define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
#define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
#define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
#define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
#define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
#define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
#define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
#define LCSR1 0x034 /* LCD Controller Status register 1 */
#define LCSR0 0x038 /* LCD Controller Status register 0 */
#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
#define LCSR1 0x034 /* LCD Controller Status register 1 */
#define LCSR0 0x038 /* LCD Controller Status register 0 */
#define LIIDR 0x03c /* LCD Controller Interrupt ID register */
#define TRGBR 0x040 /* TMED RGB Seed register */
#define TCR 0x044 /* TMED Control register */
#define TRGBR 0x040 /* TMED RGB Seed register */
#define TCR 0x044 /* TMED Control register */
#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
#define CCR 0x090 /* Cursor Control register */
#define OVL1C1 0x050 /* Overlay 1 Control register 1 */
#define OVL1C2 0x060 /* Overlay 1 Control register 2 */
#define OVL2C1 0x070 /* Overlay 2 Control register 1 */
#define OVL2C2 0x080 /* Overlay 2 Control register 2 */
#define CCR 0x090 /* Cursor Control register */
#define CMDCR 0x100 /* Command Control register */
#define PRSR 0x104 /* Panel Read Status register */
#define CMDCR 0x100 /* Command Control register */
#define PRSR 0x104 /* Panel Read Status register */
#define PXA_LCDDMA_CHANS 7
#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
#define DMA_FSADR 0x04 /* Frame Source Address register */
#define DMA_FIDR 0x08 /* Frame ID register */
#define DMA_LDCMD 0x0c /* Command register */
#define PXA_LCDDMA_CHANS 7
#define DMA_FDADR 0x00 /* Frame Descriptor Address register */
#define DMA_FSADR 0x04 /* Frame Source Address register */
#define DMA_FIDR 0x08 /* Frame ID register */
#define DMA_LDCMD 0x0c /* Command register */
/* LCD Buffer Strength Control register */
#define BSCNTR 0x04000054
#define BSCNTR 0x04000054
/* Bitfield masks */
#define LCCR0_ENB (1 << 0)
#define LCCR0_CMS (1 << 1)
#define LCCR0_SDS (1 << 2)
#define LCCR0_LDM (1 << 3)
#define LCCR0_SOFM0 (1 << 4)
#define LCCR0_IUM (1 << 5)
#define LCCR0_EOFM0 (1 << 6)
#define LCCR0_PAS (1 << 7)
#define LCCR0_DPD (1 << 9)
#define LCCR0_DIS (1 << 10)
#define LCCR0_QDM (1 << 11)
#define LCCR0_PDD (0xff << 12)
#define LCCR0_BSM0 (1 << 20)
#define LCCR0_OUM (1 << 21)
#define LCCR0_LCDT (1 << 22)
#define LCCR0_RDSTM (1 << 23)
#define LCCR0_CMDIM (1 << 24)
#define LCCR0_OUC (1 << 25)
#define LCCR0_LDDALT (1 << 26)
#define LCCR1_PPL(x) ((x) & 0x3ff)
#define LCCR2_LPP(x) ((x) & 0x3ff)
#define LCCR3_API (15 << 16)
#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
#define LCCR4_K1(x) (((x) >> 0) & 7)
#define LCCR4_K2(x) (((x) >> 3) & 7)
#define LCCR4_K3(x) (((x) >> 6) & 7)
#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
#define LCCR5_SOFM(ch) (1 << (ch - 1))
#define LCCR5_EOFM(ch) (1 << (ch + 7))
#define LCCR5_BSM(ch) (1 << (ch + 15))
#define LCCR5_IUM(ch) (1 << (ch + 23))
#define OVLC1_EN (1 << 31)
#define CCR_CEN (1 << 31)
#define FBR_BRA (1 << 0)
#define FBR_BINT (1 << 1)
#define FBR_SRCADDR (0xfffffff << 4)
#define LCSR0_LDD (1 << 0)
#define LCSR0_SOF0 (1 << 1)
#define LCSR0_BER (1 << 2)
#define LCSR0_ABC (1 << 3)
#define LCSR0_IU0 (1 << 4)
#define LCSR0_IU1 (1 << 5)
#define LCSR0_OU (1 << 6)
#define LCSR0_QD (1 << 7)
#define LCSR0_EOF0 (1 << 8)
#define LCSR0_BS0 (1 << 9)
#define LCSR0_SINT (1 << 10)
#define LCSR0_RDST (1 << 11)
#define LCSR0_CMDINT (1 << 12)
#define LCSR0_BERCH(x) (((x) & 7) << 28)
#define LCSR1_SOF(ch) (1 << (ch - 1))
#define LCSR1_EOF(ch) (1 << (ch + 7))
#define LCSR1_BS(ch) (1 << (ch + 15))
#define LCSR1_IU(ch) (1 << (ch + 23))
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
#define LDCMD_EOFINT (1 << 21)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_PAL (1 << 26)
#define LCCR0_ENB (1 << 0)
#define LCCR0_CMS (1 << 1)
#define LCCR0_SDS (1 << 2)
#define LCCR0_LDM (1 << 3)
#define LCCR0_SOFM0 (1 << 4)
#define LCCR0_IUM (1 << 5)
#define LCCR0_EOFM0 (1 << 6)
#define LCCR0_PAS (1 << 7)
#define LCCR0_DPD (1 << 9)
#define LCCR0_DIS (1 << 10)
#define LCCR0_QDM (1 << 11)
#define LCCR0_PDD (0xff << 12)
#define LCCR0_BSM0 (1 << 20)
#define LCCR0_OUM (1 << 21)
#define LCCR0_LCDT (1 << 22)
#define LCCR0_RDSTM (1 << 23)
#define LCCR0_CMDIM (1 << 24)
#define LCCR0_OUC (1 << 25)
#define LCCR0_LDDALT (1 << 26)
#define LCCR1_PPL(x) ((x) & 0x3ff)
#define LCCR2_LPP(x) ((x) & 0x3ff)
#define LCCR3_API (15 << 16)
#define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
#define LCCR3_PDFOR(x) (((x) >> 30) & 3)
#define LCCR4_K1(x) (((x) >> 0) & 7)
#define LCCR4_K2(x) (((x) >> 3) & 7)
#define LCCR4_K3(x) (((x) >> 6) & 7)
#define LCCR4_PALFOR(x) (((x) >> 15) & 3)
#define LCCR5_SOFM(ch) (1 << (ch - 1))
#define LCCR5_EOFM(ch) (1 << (ch + 7))
#define LCCR5_BSM(ch) (1 << (ch + 15))
#define LCCR5_IUM(ch) (1 << (ch + 23))
#define OVLC1_EN (1 << 31)
#define CCR_CEN (1 << 31)
#define FBR_BRA (1 << 0)
#define FBR_BINT (1 << 1)
#define FBR_SRCADDR (0xfffffff << 4)
#define LCSR0_LDD (1 << 0)
#define LCSR0_SOF0 (1 << 1)
#define LCSR0_BER (1 << 2)
#define LCSR0_ABC (1 << 3)
#define LCSR0_IU0 (1 << 4)
#define LCSR0_IU1 (1 << 5)
#define LCSR0_OU (1 << 6)
#define LCSR0_QD (1 << 7)
#define LCSR0_EOF0 (1 << 8)
#define LCSR0_BS0 (1 << 9)
#define LCSR0_SINT (1 << 10)
#define LCSR0_RDST (1 << 11)
#define LCSR0_CMDINT (1 << 12)
#define LCSR0_BERCH(x) (((x) & 7) << 28)
#define LCSR1_SOF(ch) (1 << (ch - 1))
#define LCSR1_EOF(ch) (1 << (ch + 7))
#define LCSR1_BS(ch) (1 << (ch + 15))
#define LCSR1_IU(ch) (1 << (ch + 23))
#define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
#define LDCMD_EOFINT (1 << 21)
#define LDCMD_SOFINT (1 << 22)
#define LDCMD_PAL (1 << 26)
/* Size of a pixel in the QEMU UI output surface, in bytes */
#define DEST_PIXEL_WIDTH 4
@ -788,7 +788,7 @@ static uint64_t pxa2xx_lcdc_read(void *opaque, hwaddr offset,
case TCR:
return s->tcr;
case 0x200 ... 0x1000: /* DMA per-channel registers */
case 0x200 ... 0x1000: /* DMA per-channel registers */
ch = (offset - 0x200) >> 4;
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
goto fail;
@ -938,7 +938,7 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offset,
s->tcr = value & 0x7fff;
break;
case 0x200 ... 0x1000: /* DMA per-channel registers */
case 0x200 ... 0x1000: /* DMA per-channel registers */
ch = (offset - 0x200) >> 4;
if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
goto fail;

6
hw/display/vga_regs.h
View File

@ -4,9 +4,9 @@
* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
*
* Copyright history from vga16fb.c:
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this

258
hw/display/xenfb.c
View File

@ -76,7 +76,7 @@ struct XenFB {
int do_resize;
struct {
int x,y,w,h;
int x,y,w,h;
} up_rects[UP_QUEUE];
int up_count;
int up_fullscreen;
@ -116,32 +116,32 @@ static void common_unbind(struct common *c)
xen_pv_unbind_evtchn(&c->xendev);
if (c->page) {
xenforeignmemory_unmap(xen_fmem, c->page, 1);
c->page = NULL;
c->page = NULL;
}
}
/* -------------------------------------------------------------------- */
/* Send an event to the keyboard frontend driver */
static int xenfb_kbd_event(struct XenInput *xenfb,
union xenkbd_in_event *event)
union xenkbd_in_event *event)
{
struct xenkbd_page *page = xenfb->c.page;
uint32_t prod;
if (xenfb->c.xendev.be_state != XenbusStateConnected)
return 0;
return 0;
if (!page)
return 0;
prod = page->in_prod;
if (prod - page->in_cons == XENKBD_IN_RING_LEN) {
errno = EAGAIN;
return -1;
errno = EAGAIN;
return -1;
}
xen_mb(); /* ensure ring space available */
xen_mb(); /* ensure ring space available */
XENKBD_IN_RING_REF(page, prod) = *event;
xen_wmb(); /* ensure ring contents visible */
xen_wmb(); /* ensure ring contents visible */
page->in_prod = prod + 1;
return xen_pv_send_notify(&xenfb->c.xendev);
}
@ -161,7 +161,7 @@ static int xenfb_send_key(struct XenInput *xenfb, bool down, int keycode)
/* Send a relative mouse movement event */
static int xenfb_send_motion(struct XenInput *xenfb,
int rel_x, int rel_y, int rel_z)
int rel_x, int rel_y, int rel_z)
{
union xenkbd_in_event event;
@ -176,7 +176,7 @@ static int xenfb_send_motion(struct XenInput *xenfb,
/* Send an absolute mouse movement event */
static int xenfb_send_position(struct XenInput *xenfb,
int abs_x, int abs_y, int z)
int abs_x, int abs_y, int z)
{
union xenkbd_in_event event;
@ -354,7 +354,7 @@ static int input_initialise(struct XenLegacyDevice *xendev)
rc = common_bind(&in->c);
if (rc != 0)
return rc;
return rc;
return 0;
}
@ -415,7 +415,7 @@ static void input_event(struct XenLegacyDevice *xendev)
/* We don't understand any keyboard events, so just ignore them. */
if (page->out_prod == page->out_cons)
return;
return;
page->out_cons = page->out_prod;
xen_pv_send_notify(&xenfb->c.xendev);
}
@ -429,7 +429,7 @@ static void xenfb_copy_mfns(int mode, int count, xen_pfn_t *dst, void *src)
int i;
for (i = 0; i < count; i++)
dst[i] = (mode == 32) ? src32[i] : src64[i];
dst[i] = (mode == 32) ? src32[i] : src64[i];
}
static int xenfb_map_fb(struct XenFB *xenfb)
@ -447,43 +447,43 @@ static int xenfb_map_fb(struct XenFB *xenfb)
mode = sizeof(unsigned long) * 8;
if (!protocol) {
/*
* Undefined protocol, some guesswork needed.
*
* Old frontends which don't set the protocol use
* one page directory only, thus pd[1] must be zero.
* pd[1] of the 32bit struct layout and the lower
* 32 bits of pd[0] of the 64bit struct layout have
* the same location, so we can check that ...
*/
uint32_t *ptr32 = NULL;
uint32_t *ptr64 = NULL;
/*
* Undefined protocol, some guesswork needed.
*
* Old frontends which don't set the protocol use
* one page directory only, thus pd[1] must be zero.
* pd[1] of the 32bit struct layout and the lower
* 32 bits of pd[0] of the 64bit struct layout have
* the same location, so we can check that ...
*/
uint32_t *ptr32 = NULL;
uint32_t *ptr64 = NULL;
#if defined(__i386__)
ptr32 = (void*)page->pd;
ptr64 = ((void*)page->pd) + 4;
ptr32 = (void*)page->pd;
ptr64 = ((void*)page->pd) + 4;
#elif defined(__x86_64__)
ptr32 = ((void*)page->pd) - 4;
ptr64 = (void*)page->pd;
ptr32 = ((void*)page->pd) - 4;
ptr64 = (void*)page->pd;
#endif
if (ptr32) {
if (ptr32[1] == 0) {
mode = 32;
pd = ptr32;
} else {
mode = 64;
pd = ptr64;
}
}
if (ptr32) {
if (ptr32[1] == 0) {
mode = 32;
pd = ptr32;
} else {
mode = 64;
pd = ptr64;
}
}
#if defined(__x86_64__)
} else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_32) == 0) {
/* 64bit dom0, 32bit domU */
mode = 32;
pd = ((void*)page->pd) - 4;
/* 64bit dom0, 32bit domU */
mode = 32;
pd = ((void*)page->pd) - 4;
#elif defined(__i386__)
} else if (strcmp(protocol, XEN_IO_PROTO_ABI_X86_64) == 0) {
/* 32bit dom0, 64bit domU */
mode = 64;
pd = ((void*)page->pd) + 4;
/* 32bit dom0, 64bit domU */
mode = 64;
pd = ((void*)page->pd) + 4;
#endif
}
@ -503,14 +503,14 @@ static int xenfb_map_fb(struct XenFB *xenfb)
map = xenforeignmemory_map(xen_fmem, xenfb->c.xendev.dom,
PROT_READ, n_fbdirs, pgmfns, NULL);
if (map == NULL)
goto out;
goto out;
xenfb_copy_mfns(mode, xenfb->fbpages, fbmfns, map);
xenforeignmemory_unmap(xen_fmem, map, n_fbdirs);
xenfb->pixels = xenforeignmemory_map(xen_fmem, xenfb->c.xendev.dom,
PROT_READ, xenfb->fbpages, fbmfns, NULL);
if (xenfb->pixels == NULL)
goto out;
goto out;
ret = 0; /* all is fine */
@ -589,35 +589,35 @@ static int xenfb_configure_fb(struct XenFB *xenfb, size_t fb_len_lim,
/* A convenient function for munging pixels between different depths */
#define BLT(SRC_T,DST_T,RSB,GSB,BSB,RDB,GDB,BDB) \
for (line = y ; line < (y+h) ; line++) { \
SRC_T *src = (SRC_T *)(xenfb->pixels \
+ xenfb->offset \
+ (line * xenfb->row_stride) \
+ (x * xenfb->depth / 8)); \
DST_T *dst = (DST_T *)(data \
+ (line * linesize) \
+ (x * bpp / 8)); \
int col; \
const int RSS = 32 - (RSB + GSB + BSB); \
const int GSS = 32 - (GSB + BSB); \
const int BSS = 32 - (BSB); \
const uint32_t RSM = (~0U) << (32 - RSB); \
const uint32_t GSM = (~0U) << (32 - GSB); \
const uint32_t BSM = (~0U) << (32 - BSB); \
const int RDS = 32 - (RDB + GDB + BDB); \
const int GDS = 32 - (GDB + BDB); \
const int BDS = 32 - (BDB); \
const uint32_t RDM = (~0U) << (32 - RDB); \
const uint32_t GDM = (~0U) << (32 - GDB); \
const uint32_t BDM = (~0U) << (32 - BDB); \
for (col = x ; col < (x+w) ; col++) { \
uint32_t spix = *src; \
*dst = (((spix << RSS) & RSM & RDM) >> RDS) | \
(((spix << GSS) & GSM & GDM) >> GDS) | \
(((spix << BSS) & BSM & BDM) >> BDS); \
src = (SRC_T *) ((unsigned long) src + xenfb->depth / 8); \
dst = (DST_T *) ((unsigned long) dst + bpp / 8); \
} \
for (line = y ; line < (y+h) ; line++) { \
SRC_T *src = (SRC_T *)(xenfb->pixels \
+ xenfb->offset \
+ (line * xenfb->row_stride) \
+ (x * xenfb->depth / 8)); \
DST_T *dst = (DST_T *)(data \
+ (line * linesize) \
+ (x * bpp / 8)); \
int col; \
const int RSS = 32 - (RSB + GSB + BSB); \
const int GSS = 32 - (GSB + BSB); \
const int BSS = 32 - (BSB); \
const uint32_t RSM = (~0U) << (32 - RSB); \
const uint32_t GSM = (~0U) << (32 - GSB); \
const uint32_t BSM = (~0U) << (32 - BSB); \
const int RDS = 32 - (RDB + GDB + BDB); \
const int GDS = 32 - (GDB + BDB); \
const int BDS = 32 - (BDB); \
const uint32_t RDM = (~0U) << (32 - RDB); \
const uint32_t GDM = (~0U) << (32 - GDB); \
const uint32_t BDM = (~0U) << (32 - BDB); \
for (col = x ; col < (x+w) ; col++) { \
uint32_t spix = *src; \
*dst = (((spix << RSS) & RSM & RDM) >> RDS) | \
(((spix << GSS) & GSM & GDM) >> GDS) | \
(((spix << BSS) & BSM & BDM) >> BDS); \
src = (SRC_T *) ((unsigned long) src + xenfb->depth / 8); \
dst = (DST_T *) ((unsigned long) dst + bpp / 8); \
} \
}
@ -657,7 +657,7 @@ static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h)
break;
default:
oops = 1;
}
}
}
if (oops) /* should not happen */
xen_pv_printf(&xenfb->c.xendev, 0, "%s: oops: convert %d -> %d bpp?\n",
@ -816,60 +816,60 @@ static void xenfb_handle_events(struct XenFB *xenfb)
if (prod - out_cons > XENFB_OUT_RING_LEN) {
return;
}
xen_rmb(); /* ensure we see ring contents up to prod */
xen_rmb(); /* ensure we see ring contents up to prod */
for (cons = out_cons; cons != prod; cons++) {
union xenfb_out_event *event = &XENFB_OUT_RING_REF(page, cons);
union xenfb_out_event *event = &XENFB_OUT_RING_REF(page, cons);
uint8_t type = event->type;
int x, y, w, h;
int x, y, w, h;
switch (type) {
case XENFB_TYPE_UPDATE:
if (xenfb->up_count == UP_QUEUE)
xenfb->up_fullscreen = 1;
if (xenfb->up_fullscreen)
break;
x = MAX(event->update.x, 0);
y = MAX(event->update.y, 0);
w = MIN(event->update.width, xenfb->width - x);
h = MIN(event->update.height, xenfb->height - y);
if (w < 0 || h < 0) {
switch (type) {
case XENFB_TYPE_UPDATE:
if (xenfb->up_count == UP_QUEUE)
xenfb->up_fullscreen = 1;
if (xenfb->up_fullscreen)
break;
x = MAX(event->update.x, 0);
y = MAX(event->update.y, 0);
w = MIN(event->update.width, xenfb->width - x);
h = MIN(event->update.height, xenfb->height - y);
if (w < 0 || h < 0) {
xen_pv_printf(&xenfb->c.xendev, 1, "bogus update ignored\n");
break;
}
if (x != event->update.x ||
break;
}
if (x != event->update.x ||
y != event->update.y ||
w != event->update.width ||
h != event->update.height) {
w != event->update.width ||
h != event->update.height) {
xen_pv_printf(&xenfb->c.xendev, 1, "bogus update clipped\n");
}
if (w == xenfb->width && h > xenfb->height / 2) {
/* scroll detector: updated more than 50% of the lines,
* don't bother keeping track of the rectangles then */
xenfb->up_fullscreen = 1;
} else {
xenfb->up_rects[xenfb->up_count].x = x;
xenfb->up_rects[xenfb->up_count].y = y;
xenfb->up_rects[xenfb->up_count].w = w;
xenfb->up_rects[xenfb->up_count].h = h;
xenfb->up_count++;
}
break;
}
if (w == xenfb->width && h > xenfb->height / 2) {
/* scroll detector: updated more than 50% of the lines,
* don't bother keeping track of the rectangles then */
xenfb->up_fullscreen = 1;
} else {
xenfb->up_rects[xenfb->up_count].x = x;
xenfb->up_rects[xenfb->up_count].y = y;
xenfb->up_rects[xenfb->up_count].w = w;
xenfb->up_rects[xenfb->up_count].h = h;
xenfb->up_count++;
}
break;
#ifdef XENFB_TYPE_RESIZE
case XENFB_TYPE_RESIZE:
if (xenfb_configure_fb(xenfb, xenfb->fb_len,
event->resize.width,
event->resize.height,
event->resize.depth,
xenfb->fb_len,
event->resize.offset,
event->resize.stride) < 0)
break;
xenfb_invalidate(xenfb);
break;
case XENFB_TYPE_RESIZE:
if (xenfb_configure_fb(xenfb, xenfb->fb_len,
event->resize.width,
event->resize.height,
event->resize.depth,
xenfb->fb_len,
event->resize.offset,
event->resize.stride) < 0)
break;
xenfb_invalidate(xenfb);
break;
#endif
}
}
}
xen_mb(); /* ensure we're done with ring contents */
xen_mb(); /* ensure we're done with ring contents */
page->out_cons = cons;
}
@ -889,32 +889,32 @@ static int fb_initialise(struct XenLegacyDevice *xendev)
int rc;
if (xenstore_read_fe_int(xendev, "videoram", &videoram) == -1)
videoram = 0;
videoram = 0;
rc = common_bind(&fb->c);
if (rc != 0)
return rc;
return rc;
fb_page = fb->c.page;
rc = xenfb_configure_fb(fb, videoram * MiB,
fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length);
fb_page->width, fb_page->height, fb_page->depth,
fb_page->mem_length, 0, fb_page->line_length);
if (rc != 0)
return rc;
return rc;
rc = xenfb_map_fb(fb);
if (rc != 0)
return rc;
return rc;
fb->con = graphic_console_init(NULL, 0, &xenfb_ops, fb);
if (xenstore_read_fe_int(xendev, "feature-update", &fb->feature_update) == -1)
fb->feature_update = 0;
fb->feature_update = 0;
if (fb->feature_update)
xenstore_write_be_int(xendev, "request-update", 1);
xenstore_write_be_int(xendev, "request-update", 1);
xen_pv_printf(xendev, 1, "feature-update=%d, videoram=%d\n",
fb->feature_update, videoram);
fb->feature_update, videoram);
return 0;
}

4
hw/s390x/s390-pci-kvm.c
View File

@ -22,9 +22,7 @@
bool s390_pci_kvm_interp_allowed(void)
{
return (kvm_s390_get_zpci_op() && !s390_is_pv() &&
!object_property_get_bool(OBJECT(qdev_get_machine()),
"zpcii-disable", NULL));
return kvm_s390_get_zpci_op() && !s390_is_pv();
}
int s390_pci_kvm_aif_enable(S390PCIBusDevice *pbdev, ZpciFib *fib, bool assist)

29
hw/s390x/s390-virtio-ccw.c
View File

@ -627,21 +627,6 @@ static inline void machine_set_dea_key_wrap(Object *obj, bool value,
ms->dea_key_wrap = value;
}
static inline bool machine_get_zpcii_disable(Object *obj, Error **errp)
{
S390CcwMachineState *ms = S390_CCW_MACHINE(obj);
return ms->zpcii_disable;
}
static inline void machine_set_zpcii_disable(Object *obj, bool value,
Error **errp)
{
S390CcwMachineState *ms = S390_CCW_MACHINE(obj);
ms->zpcii_disable = value;
}
static S390CcwMachineClass *current_mc;
/*
@ -778,12 +763,6 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data)
"Up to 8 chars in set of [A-Za-z0-9. ] (lower case chars converted"
" to upper case) to pass to machine loader, boot manager,"
" and guest kernel");
object_class_property_add_bool(oc, "zpcii-disable",
machine_get_zpcii_disable,
machine_set_zpcii_disable);
object_class_property_set_description(oc, "zpcii-disable",
"disable zPCI interpretation facilties");
}
static inline void s390_machine_initfn(Object *obj)
@ -792,7 +771,6 @@ static inline void s390_machine_initfn(Object *obj)
ms->aes_key_wrap = true;
ms->dea_key_wrap = true;
ms->zpcii_disable = false;
}
static const TypeInfo ccw_machine_info = {
@ -857,20 +835,23 @@ DEFINE_CCW_MACHINE(7_2, "7.2", true);
static void ccw_machine_7_1_instance_options(MachineState *machine)
{
static const S390FeatInit qemu_cpu_feat = { S390_FEAT_LIST_QEMU_V7_1 };
S390CcwMachineState *ms = S390_CCW_MACHINE(machine);
ccw_machine_7_2_instance_options(machine);
s390_cpudef_featoff_greater(16, 1, S390_FEAT_PAIE);
s390_set_qemu_cpu_model(0x8561, 15, 1, qemu_cpu_feat);
ms->zpcii_disable = true;
}
static void ccw_machine_7_1_class_options(MachineClass *mc)
{
S390CcwMachineClass *s390mc = S390_CCW_MACHINE_CLASS(mc);
static GlobalProperty compat[] = {
{ TYPE_S390_PCI_DEVICE, "interpret", "off", },
{ TYPE_S390_PCI_DEVICE, "forwarding-assist", "off", },
};
ccw_machine_7_2_class_options(mc);
compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
s390mc->max_threads = S390_MAX_CPUS;
}
DEFINE_CCW_MACHINE(7_1, "7.1", false);

78
hw/usb/dev-hub.c
View File

@ -54,44 +54,44 @@ struct USBHubState {
#define TYPE_USB_HUB "usb-hub"
OBJECT_DECLARE_SIMPLE_TYPE(USBHubState, USB_HUB)
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
#define PORT_STAT_CONNECTION 0x0001
#define PORT_STAT_ENABLE 0x0002
#define PORT_STAT_SUSPEND 0x0004
#define PORT_STAT_OVERCURRENT 0x0008
#define PORT_STAT_RESET 0x0010
#define PORT_STAT_POWER 0x0100
#define PORT_STAT_LOW_SPEED 0x0200
#define PORT_STAT_CONNECTION 0x0001
#define PORT_STAT_ENABLE 0x0002
#define PORT_STAT_SUSPEND 0x0004
#define PORT_STAT_OVERCURRENT 0x0008
#define PORT_STAT_RESET 0x0010
#define PORT_STAT_POWER 0x0100
#define PORT_STAT_LOW_SPEED 0x0200
#define PORT_STAT_HIGH_SPEED 0x0400
#define PORT_STAT_TEST 0x0800
#define PORT_STAT_INDICATOR 0x1000
#define PORT_STAT_C_CONNECTION 0x0001
#define PORT_STAT_C_ENABLE 0x0002
#define PORT_STAT_C_SUSPEND 0x0004
#define PORT_STAT_C_OVERCURRENT 0x0008
#define PORT_STAT_C_RESET 0x0010
#define PORT_STAT_C_CONNECTION 0x0001
#define PORT_STAT_C_ENABLE 0x0002
#define PORT_STAT_C_SUSPEND 0x0004
#define PORT_STAT_C_OVERCURRENT 0x0008
#define PORT_STAT_C_RESET 0x0010
#define PORT_CONNECTION 0
#define PORT_ENABLE 1
#define PORT_SUSPEND 2
#define PORT_OVERCURRENT 3
#define PORT_RESET 4
#define PORT_POWER 8
#define PORT_LOWSPEED 9
#define PORT_HIGHSPEED 10
#define PORT_C_CONNECTION 16
#define PORT_C_ENABLE 17
#define PORT_C_SUSPEND 18
#define PORT_C_OVERCURRENT 19
#define PORT_C_RESET 20
#define PORT_CONNECTION 0
#define PORT_ENABLE 1
#define PORT_SUSPEND 2
#define PORT_OVERCURRENT 3
#define PORT_RESET 4
#define PORT_POWER 8
#define PORT_LOWSPEED 9
#define PORT_HIGHSPEED 10
#define PORT_C_CONNECTION 16
#define PORT_C_ENABLE 17
#define PORT_C_SUSPEND 18
#define PORT_C_OVERCURRENT 19
#define PORT_C_RESET 20
#define PORT_TEST 21
#define PORT_INDICATOR 22
@ -155,13 +155,13 @@ static const USBDesc desc_hub = {
static const uint8_t qemu_hub_hub_descriptor[] =
{
0x00, /* u8 bLength; patched in later */
0x29, /* u8 bDescriptorType; Hub-descriptor */
0x00, /* u8 bNbrPorts; (patched later) */
0x0a, /* u16 wHubCharacteristics; */
0x00, /* (per-port OC, no power switching) */
0x01, /* u8 bPwrOn2pwrGood; 2ms */
0x00 /* u8 bHubContrCurrent; 0 mA */
0x00, /* u8 bLength; patched in later */
0x29, /* u8 bDescriptorType; Hub-descriptor */
0x00, /* u8 bNbrPorts; (patched later) */
0x0a, /* u16 wHubCharacteristics; */
0x00, /* (per-port OC, no power switching) */
0x01, /* u8 bPwrOn2pwrGood; 2ms */
0x00 /* u8 bHubContrCurrent; 0 mA */
/* DeviceRemovable and PortPwrCtrlMask patched in later */
};

286
hw/usb/dev-network.c
View File

@ -52,7 +52,7 @@
#define RNDIS_PRODUCT_NUM 0xa4a2 /* Ethernet/RNDIS Gadget */
enum usbstring_idx {
STRING_MANUFACTURER = 1,
STRING_MANUFACTURER = 1,
STRING_PRODUCT,
STRING_ETHADDR,
STRING_DATA,
@ -64,39 +64,39 @@ enum usbstring_idx {
STRING_SERIALNUMBER,
};
#define DEV_CONFIG_VALUE 1 /* CDC or a subset */
#define DEV_RNDIS_CONFIG_VALUE 2 /* RNDIS; optional */
#define DEV_CONFIG_VALUE 1 /* CDC or a subset */
#define DEV_RNDIS_CONFIG_VALUE 2 /* RNDIS; optional */
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_VENDOR 0xff
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_VENDOR 0xff
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
#define USB_CDC_NETWORK_CONNECTION 0x00
#define USB_CDC_NETWORK_CONNECTION 0x00
#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
#define STATUS_BYTECOUNT 16 /* 8 byte header + data */
#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */
#define STATUS_BYTECOUNT 16 /* 8 byte header + data */
#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
static const USBDescStrings usb_net_stringtable = {
[STRING_MANUFACTURER] = "QEMU",
@ -306,57 +306,57 @@ static const USBDesc desc_net = {
/*
* RNDIS Definitions - in theory not specific to USB.
*/
#define RNDIS_MAXIMUM_FRAME_SIZE 1518
#define RNDIS_MAX_TOTAL_SIZE 1558
#define RNDIS_MAXIMUM_FRAME_SIZE 1518
#define RNDIS_MAX_TOTAL_SIZE 1558
/* Remote NDIS Versions */
#define RNDIS_MAJOR_VERSION 1
#define RNDIS_MINOR_VERSION 0
#define RNDIS_MAJOR_VERSION 1
#define RNDIS_MINOR_VERSION 0
/* Status Values */
#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
#define RNDIS_STATUS_FAILURE 0xc0000001U /* Unspecified error */
#define RNDIS_STATUS_INVALID_DATA 0xc0010015U /* Invalid data */
#define RNDIS_STATUS_NOT_SUPPORTED 0xc00000bbU /* Unsupported request */
#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000bU /* Device connected */
#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000cU /* Device disconnected */
#define RNDIS_STATUS_SUCCESS 0x00000000U /* Success */
#define RNDIS_STATUS_FAILURE 0xc0000001U /* Unspecified error */
#define RNDIS_STATUS_INVALID_DATA 0xc0010015U /* Invalid data */
#define RNDIS_STATUS_NOT_SUPPORTED 0xc00000bbU /* Unsupported request */
#define RNDIS_STATUS_MEDIA_CONNECT 0x4001000bU /* Device connected */
#define RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000cU /* Device disconnected */
/* Message Set for Connectionless (802.3) Devices */
enum {
RNDIS_PACKET_MSG = 1,
RNDIS_INITIALIZE_MSG = 2, /* Initialize device */
RNDIS_HALT_MSG = 3,
RNDIS_QUERY_MSG = 4,
RNDIS_SET_MSG = 5,
RNDIS_RESET_MSG = 6,
RNDIS_INDICATE_STATUS_MSG = 7,
RNDIS_KEEPALIVE_MSG = 8,
RNDIS_PACKET_MSG = 1,
RNDIS_INITIALIZE_MSG = 2, /* Initialize device */
RNDIS_HALT_MSG = 3,
RNDIS_QUERY_MSG = 4,
RNDIS_SET_MSG = 5,
RNDIS_RESET_MSG = 6,
RNDIS_INDICATE_STATUS_MSG = 7,
RNDIS_KEEPALIVE_MSG = 8,
};
/* Message completion */
enum {
RNDIS_INITIALIZE_CMPLT = 0x80000002U,
RNDIS_QUERY_CMPLT = 0x80000004U,
RNDIS_SET_CMPLT = 0x80000005U,
RNDIS_RESET_CMPLT = 0x80000006U,
RNDIS_KEEPALIVE_CMPLT = 0x80000008U,
RNDIS_INITIALIZE_CMPLT = 0x80000002U,
RNDIS_QUERY_CMPLT = 0x80000004U,
RNDIS_SET_CMPLT = 0x80000005U,
RNDIS_RESET_CMPLT = 0x80000006U,
RNDIS_KEEPALIVE_CMPLT = 0x80000008U,
};
/* Device Flags */
enum {
RNDIS_DF_CONNECTIONLESS = 1,
RNDIS_DF_CONNECTIONORIENTED = 2,
RNDIS_DF_CONNECTIONLESS = 1,
RNDIS_DF_CONNECTIONORIENTED = 2,
};
#define RNDIS_MEDIUM_802_3 0x00000000U
#define RNDIS_MEDIUM_802_3 0x00000000U
/* from drivers/net/sk98lin/h/skgepnmi.h */
#define OID_PNP_CAPABILITIES 0xfd010100
#define OID_PNP_SET_POWER 0xfd010101
#define OID_PNP_QUERY_POWER 0xfd010102
#define OID_PNP_ADD_WAKE_UP_PATTERN 0xfd010103
#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xfd010104
#define OID_PNP_ENABLE_WAKE_UP 0xfd010106
#define OID_PNP_CAPABILITIES 0xfd010100
#define OID_PNP_SET_POWER 0xfd010101
#define OID_PNP_QUERY_POWER 0xfd010102
#define OID_PNP_ADD_WAKE_UP_PATTERN 0xfd010103
#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xfd010104
#define OID_PNP_ENABLE_WAKE_UP 0xfd010106
typedef uint32_t le32;
@ -494,88 +494,88 @@ enum rndis_state
/* from ndis.h */
enum ndis_oid {
/* Required Object IDs (OIDs) */
OID_GEN_SUPPORTED_LIST = 0x00010101,
OID_GEN_HARDWARE_STATUS = 0x00010102,
OID_GEN_MEDIA_SUPPORTED = 0x00010103,
OID_GEN_MEDIA_IN_USE = 0x00010104,
OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105,
OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106,
OID_GEN_LINK_SPEED = 0x00010107,
OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108,
OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109,
OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010a,
OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010b,
OID_GEN_VENDOR_ID = 0x0001010c,
OID_GEN_VENDOR_DESCRIPTION = 0x0001010d,
OID_GEN_CURRENT_PACKET_FILTER = 0x0001010e,
OID_GEN_CURRENT_LOOKAHEAD = 0x0001010f,
OID_GEN_DRIVER_VERSION = 0x00010110,
OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111,
OID_GEN_PROTOCOL_OPTIONS = 0x00010112,
OID_GEN_MAC_OPTIONS = 0x00010113,
OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114,
OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115,
OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116,
OID_GEN_SUPPORTED_GUIDS = 0x00010117,
OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118,
OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119,
OID_GEN_MACHINE_NAME = 0x0001021a,
OID_GEN_RNDIS_CONFIG_PARAMETER = 0x0001021b,
OID_GEN_VLAN_ID = 0x0001021c,
OID_GEN_SUPPORTED_LIST = 0x00010101,
OID_GEN_HARDWARE_STATUS = 0x00010102,
OID_GEN_MEDIA_SUPPORTED = 0x00010103,
OID_GEN_MEDIA_IN_USE = 0x00010104,
OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105,
OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106,
OID_GEN_LINK_SPEED = 0x00010107,
OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108,
OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109,
OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010a,
OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010b,
OID_GEN_VENDOR_ID = 0x0001010c,
OID_GEN_VENDOR_DESCRIPTION = 0x0001010d,
OID_GEN_CURRENT_PACKET_FILTER = 0x0001010e,
OID_GEN_CURRENT_LOOKAHEAD = 0x0001010f,
OID_GEN_DRIVER_VERSION = 0x00010110,
OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111,
OID_GEN_PROTOCOL_OPTIONS = 0x00010112,
OID_GEN_MAC_OPTIONS = 0x00010113,
OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114,
OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115,
OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116,
OID_GEN_SUPPORTED_GUIDS = 0x00010117,
OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118,
OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119,
OID_GEN_MACHINE_NAME = 0x0001021a,
OID_GEN_RNDIS_CONFIG_PARAMETER = 0x0001021b,
OID_GEN_VLAN_ID = 0x0001021c,
/* Optional OIDs */
OID_GEN_MEDIA_CAPABILITIES = 0x00010201,
OID_GEN_PHYSICAL_MEDIUM = 0x00010202,
OID_GEN_MEDIA_CAPABILITIES = 0x00010201,
OID_GEN_PHYSICAL_MEDIUM = 0x00010202,
/* Required statistics OIDs */
OID_GEN_XMIT_OK = 0x00020101,
OID_GEN_RCV_OK = 0x00020102,
OID_GEN_XMIT_ERROR = 0x00020103,
OID_GEN_RCV_ERROR = 0x00020104,
OID_GEN_RCV_NO_BUFFER = 0x00020105,
OID_GEN_XMIT_OK = 0x00020101,
OID_GEN_RCV_OK = 0x00020102,
OID_GEN_XMIT_ERROR = 0x00020103,
OID_GEN_RCV_ERROR = 0x00020104,
OID_GEN_RCV_NO_BUFFER = 0x00020105,
/* Optional statistics OIDs */
OID_GEN_DIRECTED_BYTES_XMIT = 0x00020201,
OID_GEN_DIRECTED_FRAMES_XMIT = 0x00020202,
OID_GEN_MULTICAST_BYTES_XMIT = 0x00020203,
OID_GEN_MULTICAST_FRAMES_XMIT = 0x00020204,
OID_GEN_BROADCAST_BYTES_XMIT = 0x00020205,
OID_GEN_BROADCAST_FRAMES_XMIT = 0x00020206,
OID_GEN_DIRECTED_BYTES_RCV = 0x00020207,
OID_GEN_DIRECTED_FRAMES_RCV = 0x00020208,
OID_GEN_MULTICAST_BYTES_RCV = 0x00020209,
OID_GEN_MULTICAST_FRAMES_RCV = 0x0002020a,
OID_GEN_BROADCAST_BYTES_RCV = 0x0002020b,
OID_GEN_BROADCAST_FRAMES_RCV = 0x0002020c,
OID_GEN_RCV_CRC_ERROR = 0x0002020d,
OID_GEN_TRANSMIT_QUEUE_LENGTH = 0x0002020e,
OID_GEN_GET_TIME_CAPS = 0x0002020f,
OID_GEN_GET_NETCARD_TIME = 0x00020210,
OID_GEN_NETCARD_LOAD = 0x00020211,
OID_GEN_DEVICE_PROFILE = 0x00020212,
OID_GEN_INIT_TIME_MS = 0x00020213,
OID_GEN_RESET_COUNTS = 0x00020214,
OID_GEN_MEDIA_SENSE_COUNTS = 0x00020215,
OID_GEN_FRIENDLY_NAME = 0x00020216,
OID_GEN_MINIPORT_INFO = 0x00020217,
OID_GEN_RESET_VERIFY_PARAMETERS = 0x00020218,
OID_GEN_DIRECTED_BYTES_XMIT = 0x00020201,
OID_GEN_DIRECTED_FRAMES_XMIT = 0x00020202,
OID_GEN_MULTICAST_BYTES_XMIT = 0x00020203,
OID_GEN_MULTICAST_FRAMES_XMIT = 0x00020204,
OID_GEN_BROADCAST_BYTES_XMIT = 0x00020205,
OID_GEN_BROADCAST_FRAMES_XMIT = 0x00020206,
OID_GEN_DIRECTED_BYTES_RCV = 0x00020207,
OID_GEN_DIRECTED_FRAMES_RCV = 0x00020208,
OID_GEN_MULTICAST_BYTES_RCV = 0x00020209,
OID_GEN_MULTICAST_FRAMES_RCV = 0x0002020a,
OID_GEN_BROADCAST_BYTES_RCV = 0x0002020b,
OID_GEN_BROADCAST_FRAMES_RCV = 0x0002020c,
OID_GEN_RCV_CRC_ERROR = 0x0002020d,
OID_GEN_TRANSMIT_QUEUE_LENGTH = 0x0002020e,
OID_GEN_GET_TIME_CAPS = 0x0002020f,
OID_GEN_GET_NETCARD_TIME = 0x00020210,
OID_GEN_NETCARD_LOAD = 0x00020211,
OID_GEN_DEVICE_PROFILE = 0x00020212,
OID_GEN_INIT_TIME_MS = 0x00020213,
OID_GEN_RESET_COUNTS = 0x00020214,
OID_GEN_MEDIA_SENSE_COUNTS = 0x00020215,
OID_GEN_FRIENDLY_NAME = 0x00020216,
OID_GEN_MINIPORT_INFO = 0x00020217,
OID_GEN_RESET_VERIFY_PARAMETERS = 0x00020218,
/* IEEE 802.3 (Ethernet) OIDs */
OID_802_3_PERMANENT_ADDRESS = 0x01010101,
OID_802_3_CURRENT_ADDRESS = 0x01010102,
OID_802_3_MULTICAST_LIST = 0x01010103,
OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104,
OID_802_3_MAC_OPTIONS = 0x01010105,
OID_802_3_RCV_ERROR_ALIGNMENT = 0x01020101,
OID_802_3_XMIT_ONE_COLLISION = 0x01020102,
OID_802_3_XMIT_MORE_COLLISIONS = 0x01020103,
OID_802_3_XMIT_DEFERRED = 0x01020201,
OID_802_3_XMIT_MAX_COLLISIONS = 0x01020202,
OID_802_3_RCV_OVERRUN = 0x01020203,
OID_802_3_XMIT_UNDERRUN = 0x01020204,
OID_802_3_XMIT_HEARTBEAT_FAILURE = 0x01020205,
OID_802_3_XMIT_TIMES_CRS_LOST = 0x01020206,
OID_802_3_XMIT_LATE_COLLISIONS = 0x01020207,
OID_802_3_PERMANENT_ADDRESS = 0x01010101,
OID_802_3_CURRENT_ADDRESS = 0x01010102,
OID_802_3_MULTICAST_LIST = 0x01010103,
OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104,
OID_802_3_MAC_OPTIONS = 0x01010105,
OID_802_3_RCV_ERROR_ALIGNMENT = 0x01020101,
OID_802_3_XMIT_ONE_COLLISION = 0x01020102,
OID_802_3_XMIT_MORE_COLLISIONS = 0x01020103,
OID_802_3_XMIT_DEFERRED = 0x01020201,
OID_802_3_XMIT_MAX_COLLISIONS = 0x01020202,
OID_802_3_RCV_OVERRUN = 0x01020203,
OID_802_3_XMIT_UNDERRUN = 0x01020204,
OID_802_3_XMIT_HEARTBEAT_FAILURE = 0x01020205,
OID_802_3_XMIT_TIMES_CRS_LOST = 0x01020206,
OID_802_3_XMIT_LATE_COLLISIONS = 0x01020207,
};
static const uint32_t oid_supported_list[] =
@ -618,13 +618,13 @@ static const uint32_t oid_supported_list[] =
OID_802_3_XMIT_MORE_COLLISIONS,
};
#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA (1 << 0)
#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED (1 << 1)
#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND (1 << 2)
#define NDIS_MAC_OPTION_NO_LOOPBACK (1 << 3)
#define NDIS_MAC_OPTION_FULL_DUPLEX (1 << 4)
#define NDIS_MAC_OPTION_EOTX_INDICATION (1 << 5)
#define NDIS_MAC_OPTION_8021P_PRIORITY (1 << 6)
#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA (1 << 0)
#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED (1 << 1)
#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND (1 << 2)
#define NDIS_MAC_OPTION_NO_LOOPBACK (1 << 3)
#define NDIS_MAC_OPTION_FULL_DUPLEX (1 << 4)
#define NDIS_MAC_OPTION_EOTX_INDICATION (1 << 5)
#define NDIS_MAC_OPTION_8021P_PRIORITY (1 << 6)
struct rndis_response {
QTAILQ_ENTRY(rndis_response) entries;
@ -1375,12 +1375,12 @@ static void usb_net_realize(USBDevice *dev, Error **errp)
s->rndis_state = RNDIS_UNINITIALIZED;
QTAILQ_INIT(&s->rndis_resp);
s->medium = 0; /* NDIS_MEDIUM_802_3 */
s->medium = 0; /* NDIS_MEDIUM_802_3 */
s->speed = 1000000; /* 100MBps, in 100Bps units */
s->media_state = 0; /* NDIS_MEDIA_STATE_CONNECTED */;
s->media_state = 0; /* NDIS_MEDIA_STATE_CONNECTED */;
s->filter = 0;
s->vendorid = 0x1234;
s->connection = 1; /* Connected */
s->connection = 1; /* Connected */
s->intr = usb_ep_get(dev, USB_TOKEN_IN, 1);
s->bulk_in = usb_ep_get(dev, USB_TOKEN_IN, 2);

4
hw/usb/dev-wacom.c
View File

@ -36,8 +36,8 @@
#include "qom/object.h"
/* Interface requests */
#define WACOM_GET_REPORT 0x2101
#define WACOM_SET_REPORT 0x2109
#define WACOM_GET_REPORT 0x2101
#define WACOM_SET_REPORT 0x2109
struct USBWacomState {
USBDevice dev;

326
hw/usb/hcd-musb.c
View File

@ -28,227 +28,227 @@
#include "hw/hw.h"
/* Common USB registers */
#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
#define MUSB_HDRC_POWER 0x01 /* 8-bit */
#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
#define MUSB_HDRC_POWER 0x01 /* 8-bit */
#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
#define MUSB_HDRC_INTRRX 0x04
#define MUSB_HDRC_INTRTXE 0x06
#define MUSB_HDRC_INTRRXE 0x08
#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
#define MUSB_HDRC_INTRRX 0x04
#define MUSB_HDRC_INTRTXE 0x06
#define MUSB_HDRC_INTRRXE 0x08
#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
/* Per-EP registers in indexed mode */
#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
/* EP FIFOs */
#define MUSB_HDRC_FIFO 0x20
#define MUSB_HDRC_FIFO 0x20
/* Additional Control Registers */
#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
/* These are indexed */
#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
/* Some more registers */
#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
/* Added in HDRC 1.9(?) & MHDRC 1.4 */
/* ULPI pass-through */
#define MUSB_HDRC_ULPI_VBUSCTL 0x70
#define MUSB_HDRC_ULPI_REGDATA 0x74
#define MUSB_HDRC_ULPI_REGADDR 0x75
#define MUSB_HDRC_ULPI_REGCTL 0x76
#define MUSB_HDRC_ULPI_VBUSCTL 0x70
#define MUSB_HDRC_ULPI_REGDATA 0x74
#define MUSB_HDRC_ULPI_REGADDR 0x75
#define MUSB_HDRC_ULPI_REGCTL 0x76
/* Extended config & PHY control */
#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
/* Per-EP BUSCTL registers */
#define MUSB_HDRC_BUSCTL 0x80
#define MUSB_HDRC_BUSCTL 0x80
/* Per-EP registers in flat mode */
#define MUSB_HDRC_EP 0x100
#define MUSB_HDRC_EP 0x100
/* offsets to registers in flat model */
#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
/* "Bus control" registers */
#define MUSB_HDRC_TXFUNCADDR 0x00
#define MUSB_HDRC_TXHUBADDR 0x02
#define MUSB_HDRC_TXHUBPORT 0x03
#define MUSB_HDRC_TXFUNCADDR 0x00
#define MUSB_HDRC_TXHUBADDR 0x02
#define MUSB_HDRC_TXHUBPORT 0x03
#define MUSB_HDRC_RXFUNCADDR 0x04
#define MUSB_HDRC_RXHUBADDR 0x06
#define MUSB_HDRC_RXHUBPORT 0x07
#define MUSB_HDRC_RXFUNCADDR 0x04
#define MUSB_HDRC_RXHUBADDR 0x06
#define MUSB_HDRC_RXHUBPORT 0x07
/*
* MUSBHDRC Register bit masks
*/
/* POWER */
#define MGC_M_POWER_ISOUPDATE 0x80
#define MGC_M_POWER_SOFTCONN 0x40
#define MGC_M_POWER_HSENAB 0x20
#define MGC_M_POWER_HSMODE 0x10
#define MGC_M_POWER_RESET 0x08
#define MGC_M_POWER_RESUME 0x04
#define MGC_M_POWER_SUSPENDM 0x02
#define MGC_M_POWER_ENSUSPEND 0x01
#define MGC_M_POWER_ISOUPDATE 0x80
#define MGC_M_POWER_SOFTCONN 0x40
#define MGC_M_POWER_HSENAB 0x20
#define MGC_M_POWER_HSMODE 0x10
#define MGC_M_POWER_RESET 0x08
#define MGC_M_POWER_RESUME 0x04
#define MGC_M_POWER_SUSPENDM 0x02
#define MGC_M_POWER_ENSUSPEND 0x01
/* INTRUSB */
#define MGC_M_INTR_SUSPEND 0x01
#define MGC_M_INTR_RESUME 0x02
#define MGC_M_INTR_RESET 0x04
#define MGC_M_INTR_BABBLE 0x04
#define MGC_M_INTR_SOF 0x08
#define MGC_M_INTR_CONNECT 0x10
#define MGC_M_INTR_DISCONNECT 0x20
#define MGC_M_INTR_SESSREQ 0x40
#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
#define MGC_M_INTR_SUSPEND 0x01
#define MGC_M_INTR_RESUME 0x02
#define MGC_M_INTR_RESET 0x04
#define MGC_M_INTR_BABBLE 0x04
#define MGC_M_INTR_SOF 0x08
#define MGC_M_INTR_CONNECT 0x10
#define MGC_M_INTR_DISCONNECT 0x20
#define MGC_M_INTR_SESSREQ 0x40
#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
/* DEVCTL */
#define MGC_M_DEVCTL_BDEVICE 0x80
#define MGC_M_DEVCTL_FSDEV 0x40
#define MGC_M_DEVCTL_LSDEV 0x20
#define MGC_M_DEVCTL_VBUS 0x18
#define MGC_S_DEVCTL_VBUS 3
#define MGC_M_DEVCTL_HM 0x04
#define MGC_M_DEVCTL_HR 0x02
#define MGC_M_DEVCTL_SESSION 0x01
#define MGC_M_DEVCTL_BDEVICE 0x80
#define MGC_M_DEVCTL_FSDEV 0x40
#define MGC_M_DEVCTL_LSDEV 0x20
#define MGC_M_DEVCTL_VBUS 0x18
#define MGC_S_DEVCTL_VBUS 3
#define MGC_M_DEVCTL_HM 0x04
#define MGC_M_DEVCTL_HR 0x02
#define MGC_M_DEVCTL_SESSION 0x01
/* TESTMODE */
#define MGC_M_TEST_FORCE_HOST 0x80
#define MGC_M_TEST_FIFO_ACCESS 0x40
#define MGC_M_TEST_FORCE_FS 0x20
#define MGC_M_TEST_FORCE_HS 0x10
#define MGC_M_TEST_PACKET 0x08
#define MGC_M_TEST_K 0x04
#define MGC_M_TEST_J 0x02
#define MGC_M_TEST_SE0_NAK 0x01
#define MGC_M_TEST_FORCE_HOST 0x80
#define MGC_M_TEST_FIFO_ACCESS 0x40
#define MGC_M_TEST_FORCE_FS 0x20
#define MGC_M_TEST_FORCE_HS 0x10
#define MGC_M_TEST_PACKET 0x08
#define MGC_M_TEST_K 0x04
#define MGC_M_TEST_J 0x02
#define MGC_M_TEST_SE0_NAK 0x01
/* CSR0 */
#define MGC_M_CSR0_FLUSHFIFO 0x0100
#define MGC_M_CSR0_TXPKTRDY 0x0002
#define MGC_M_CSR0_RXPKTRDY 0x0001
#define MGC_M_CSR0_FLUSHFIFO 0x0100
#define MGC_M_CSR0_TXPKTRDY 0x0002
#define MGC_M_CSR0_RXPKTRDY 0x0001
/* CSR0 in Peripheral mode */
#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
#define MGC_M_CSR0_P_SENDSTALL 0x0020
#define MGC_M_CSR0_P_SETUPEND 0x0010
#define MGC_M_CSR0_P_DATAEND 0x0008
#define MGC_M_CSR0_P_SENTSTALL 0x0004
#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
#define MGC_M_CSR0_P_SENDSTALL 0x0020
#define MGC_M_CSR0_P_SETUPEND 0x0010
#define MGC_M_CSR0_P_DATAEND 0x0008
#define MGC_M_CSR0_P_SENTSTALL 0x0004
/* CSR0 in Host mode */
#define MGC_M_CSR0_H_NO_PING 0x0800
#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
#define MGC_M_CSR0_H_STATUSPKT 0x0040
#define MGC_M_CSR0_H_REQPKT 0x0020
#define MGC_M_CSR0_H_ERROR 0x0010
#define MGC_M_CSR0_H_SETUPPKT 0x0008
#define MGC_M_CSR0_H_RXSTALL 0x0004
#define MGC_M_CSR0_H_NO_PING 0x0800
#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
#define MGC_M_CSR0_H_STATUSPKT 0x0040
#define MGC_M_CSR0_H_REQPKT 0x0020
#define MGC_M_CSR0_H_ERROR 0x0010
#define MGC_M_CSR0_H_SETUPPKT 0x0008
#define MGC_M_CSR0_H_RXSTALL 0x0004
/* CONFIGDATA */
#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
/* TXCSR in Peripheral and Host mode */
#define MGC_M_TXCSR_AUTOSET 0x8000
#define MGC_M_TXCSR_ISO 0x4000
#define MGC_M_TXCSR_MODE 0x2000
#define MGC_M_TXCSR_DMAENAB 0x1000
#define MGC_M_TXCSR_FRCDATATOG 0x0800
#define MGC_M_TXCSR_DMAMODE 0x0400
#define MGC_M_TXCSR_CLRDATATOG 0x0040
#define MGC_M_TXCSR_FLUSHFIFO 0x0008
#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
#define MGC_M_TXCSR_TXPKTRDY 0x0001
#define MGC_M_TXCSR_AUTOSET 0x8000
#define MGC_M_TXCSR_ISO 0x4000
#define MGC_M_TXCSR_MODE 0x2000
#define MGC_M_TXCSR_DMAENAB 0x1000
#define MGC_M_TXCSR_FRCDATATOG 0x0800
#define MGC_M_TXCSR_DMAMODE 0x0400
#define MGC_M_TXCSR_CLRDATATOG 0x0040
#define MGC_M_TXCSR_FLUSHFIFO 0x0008
#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
#define MGC_M_TXCSR_TXPKTRDY 0x0001
/* TXCSR in Peripheral mode */
#define MGC_M_TXCSR_P_INCOMPTX 0x0080
#define MGC_M_TXCSR_P_SENTSTALL 0x0020
#define MGC_M_TXCSR_P_SENDSTALL 0x0010
#define MGC_M_TXCSR_P_UNDERRUN 0x0004
#define MGC_M_TXCSR_P_INCOMPTX 0x0080
#define MGC_M_TXCSR_P_SENTSTALL 0x0020
#define MGC_M_TXCSR_P_SENDSTALL 0x0010
#define MGC_M_TXCSR_P_UNDERRUN 0x0004
/* TXCSR in Host mode */
#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
#define MGC_M_TXCSR_H_RXSTALL 0x0020
#define MGC_M_TXCSR_H_ERROR 0x0004
#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
#define MGC_M_TXCSR_H_RXSTALL 0x0020
#define MGC_M_TXCSR_H_ERROR 0x0004
/* RXCSR in Peripheral and Host mode */
#define MGC_M_RXCSR_AUTOCLEAR 0x8000
#define MGC_M_RXCSR_DMAENAB 0x2000
#define MGC_M_RXCSR_DISNYET 0x1000
#define MGC_M_RXCSR_DMAMODE 0x0800
#define MGC_M_RXCSR_INCOMPRX 0x0100
#define MGC_M_RXCSR_CLRDATATOG 0x0080
#define MGC_M_RXCSR_FLUSHFIFO 0x0010
#define MGC_M_RXCSR_DATAERROR 0x0008
#define MGC_M_RXCSR_FIFOFULL 0x0002
#define MGC_M_RXCSR_RXPKTRDY 0x0001
#define MGC_M_RXCSR_AUTOCLEAR 0x8000
#define MGC_M_RXCSR_DMAENAB 0x2000
#define MGC_M_RXCSR_DISNYET 0x1000
#define MGC_M_RXCSR_DMAMODE 0x0800
#define MGC_M_RXCSR_INCOMPRX 0x0100
#define MGC_M_RXCSR_CLRDATATOG 0x0080
#define MGC_M_RXCSR_FLUSHFIFO 0x0010
#define MGC_M_RXCSR_DATAERROR 0x0008
#define MGC_M_RXCSR_FIFOFULL 0x0002
#define MGC_M_RXCSR_RXPKTRDY 0x0001
/* RXCSR in Peripheral mode */
#define MGC_M_RXCSR_P_ISO 0x4000
#define MGC_M_RXCSR_P_SENTSTALL 0x0040
#define MGC_M_RXCSR_P_SENDSTALL 0x0020
#define MGC_M_RXCSR_P_OVERRUN 0x0004
#define MGC_M_RXCSR_P_ISO 0x4000
#define MGC_M_RXCSR_P_SENTSTALL 0x0040
#define MGC_M_RXCSR_P_SENDSTALL 0x0020
#define MGC_M_RXCSR_P_OVERRUN 0x0004
/* RXCSR in Host mode */
#define MGC_M_RXCSR_H_AUTOREQ 0x4000
#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
#define MGC_M_RXCSR_H_RXSTALL 0x0040
#define MGC_M_RXCSR_H_REQPKT 0x0020
#define MGC_M_RXCSR_H_ERROR 0x0004
#define MGC_M_RXCSR_H_AUTOREQ 0x4000
#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
#define MGC_M_RXCSR_H_RXSTALL 0x0040
#define MGC_M_RXCSR_H_REQPKT 0x0020
#define MGC_M_RXCSR_H_ERROR 0x0004
/* HUBADDR */
#define MGC_M_HUBADDR_MULTI_TT 0x80
#define MGC_M_HUBADDR_MULTI_TT 0x80
/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
#define MGC_M_ULPI_REGCTL_REG 0x01
#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
#define MGC_M_ULPI_REGCTL_REG 0x01
/* #define MUSB_DEBUG */
@ -296,7 +296,7 @@ struct MUSBEndPoint {
uint8_t interval[2];
uint8_t config;
uint8_t fifosize;
int timeout[2]; /* Always in microframes */
int timeout[2]; /* Always in microframes */
uint8_t *buf[2];
int fifolen[2];
@ -542,7 +542,7 @@ static void musb_cb_tick1(void *opaque)
ep->delayed_cb[1](&ep->packey[1].p, opaque);
}
#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
static void musb_schedule_cb(USBPort *port, USBPacket *packey)
{
@ -1323,7 +1323,7 @@ static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
/* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
if ((value & MGC_M_POWER_HSENAB) &&
s->port.dev->speed == USB_SPEED_HIGH)
s->power |= MGC_M_POWER_HSMODE; /* Success */
s->power |= MGC_M_POWER_HSMODE; /* Success */
/* Restart frame counting. */
}
if (value & MGC_M_POWER_SUSPENDM) {

180
hw/usb/quirks-pl2303-ids.h
View File

@ -1,150 +1,150 @@
/*
* Prolific PL2303 USB to serial adaptor driver header file
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#define BENQ_VENDOR_ID 0x04a5
#define BENQ_PRODUCT_ID_S81 0x4027
#define BENQ_VENDOR_ID 0x04a5
#define BENQ_PRODUCT_ID_S81 0x4027
#define PL2303_VENDOR_ID 0x067b
#define PL2303_PRODUCT_ID 0x2303
#define PL2303_PRODUCT_ID_RSAQ2 0x04bb
#define PL2303_PRODUCT_ID_DCU11 0x1234
#define PL2303_PRODUCT_ID_PHAROS 0xaaa0
#define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
#define PL2303_PRODUCT_ID_ALDIGA 0x0611
#define PL2303_PRODUCT_ID_MMX 0x0612
#define PL2303_PRODUCT_ID_GPRS 0x0609
#define PL2303_PRODUCT_ID_HCR331 0x331a
#define PL2303_PRODUCT_ID_MOTOROLA 0x0307
#define PL2303_VENDOR_ID 0x067b
#define PL2303_PRODUCT_ID 0x2303
#define PL2303_PRODUCT_ID_RSAQ2 0x04bb
#define PL2303_PRODUCT_ID_DCU11 0x1234
#define PL2303_PRODUCT_ID_PHAROS 0xaaa0
#define PL2303_PRODUCT_ID_RSAQ3 0xaaa2
#define PL2303_PRODUCT_ID_ALDIGA 0x0611
#define PL2303_PRODUCT_ID_MMX 0x0612
#define PL2303_PRODUCT_ID_GPRS 0x0609
#define PL2303_PRODUCT_ID_HCR331 0x331a
#define PL2303_PRODUCT_ID_MOTOROLA 0x0307
#define ATEN_VENDOR_ID 0x0557
#define ATEN_VENDOR_ID2 0x0547
#define ATEN_PRODUCT_ID 0x2008
#define ATEN_VENDOR_ID 0x0557
#define ATEN_VENDOR_ID2 0x0547
#define ATEN_PRODUCT_ID 0x2008
#define IODATA_VENDOR_ID 0x04bb
#define IODATA_PRODUCT_ID 0x0a03
#define IODATA_PRODUCT_ID_RSAQ5 0x0a0e
#define IODATA_VENDOR_ID 0x04bb
#define IODATA_PRODUCT_ID 0x0a03
#define IODATA_PRODUCT_ID_RSAQ5 0x0a0e
#define ELCOM_VENDOR_ID 0x056e
#define ELCOM_PRODUCT_ID 0x5003
#define ELCOM_PRODUCT_ID_UCSGT 0x5004
#define ELCOM_VENDOR_ID 0x056e
#define ELCOM_PRODUCT_ID 0x5003
#define ELCOM_PRODUCT_ID_UCSGT 0x5004
#define ITEGNO_VENDOR_ID 0x0eba
#define ITEGNO_PRODUCT_ID 0x1080
#define ITEGNO_PRODUCT_ID_2080 0x2080
#define ITEGNO_VENDOR_ID 0x0eba
#define ITEGNO_PRODUCT_ID 0x1080
#define ITEGNO_PRODUCT_ID_2080 0x2080
#define MA620_VENDOR_ID 0x0df7
#define MA620_PRODUCT_ID 0x0620
#define MA620_VENDOR_ID 0x0df7
#define MA620_PRODUCT_ID 0x0620
#define RATOC_VENDOR_ID 0x0584
#define RATOC_PRODUCT_ID 0xb000
#define RATOC_VENDOR_ID 0x0584
#define RATOC_PRODUCT_ID 0xb000
#define TRIPP_VENDOR_ID 0x2478
#define TRIPP_PRODUCT_ID 0x2008
#define TRIPP_VENDOR_ID 0x2478
#define TRIPP_PRODUCT_ID 0x2008
#define RADIOSHACK_VENDOR_ID 0x1453
#define RADIOSHACK_PRODUCT_ID 0x4026
#define RADIOSHACK_VENDOR_ID 0x1453
#define RADIOSHACK_PRODUCT_ID 0x4026
#define DCU10_VENDOR_ID 0x0731
#define DCU10_PRODUCT_ID 0x0528
#define DCU10_VENDOR_ID 0x0731
#define DCU10_PRODUCT_ID 0x0528
#define SITECOM_VENDOR_ID 0x6189
#define SITECOM_PRODUCT_ID 0x2068
#define SITECOM_VENDOR_ID 0x6189
#define SITECOM_PRODUCT_ID 0x2068
/* Alcatel OT535/735 USB cable */
#define ALCATEL_VENDOR_ID 0x11f7
#define ALCATEL_PRODUCT_ID 0x02df
#define ALCATEL_VENDOR_ID 0x11f7
#define ALCATEL_PRODUCT_ID 0x02df
/* Samsung I330 phone cradle */
#define SAMSUNG_VENDOR_ID 0x04e8
#define SAMSUNG_PRODUCT_ID 0x8001
#define SAMSUNG_VENDOR_ID 0x04e8
#define SAMSUNG_PRODUCT_ID 0x8001
#define SIEMENS_VENDOR_ID 0x11f5
#define SIEMENS_PRODUCT_ID_SX1 0x0001
#define SIEMENS_PRODUCT_ID_X65 0x0003
#define SIEMENS_PRODUCT_ID_X75 0x0004
#define SIEMENS_PRODUCT_ID_EF81 0x0005
#define SIEMENS_VENDOR_ID 0x11f5
#define SIEMENS_PRODUCT_ID_SX1 0x0001
#define SIEMENS_PRODUCT_ID_X65 0x0003
#define SIEMENS_PRODUCT_ID_X75 0x0004
#define SIEMENS_PRODUCT_ID_EF81 0x0005
#define SYNTECH_VENDOR_ID 0x0745
#define SYNTECH_PRODUCT_ID 0x0001
#define SYNTECH_VENDOR_ID 0x0745
#define SYNTECH_PRODUCT_ID 0x0001
/* Nokia CA-42 Cable */
#define NOKIA_CA42_VENDOR_ID 0x078b
#define NOKIA_CA42_PRODUCT_ID 0x1234
#define NOKIA_CA42_VENDOR_ID 0x078b
#define NOKIA_CA42_PRODUCT_ID 0x1234
/* CA-42 CLONE Cable www.ca-42.com chipset: Prolific Technology Inc */
#define CA_42_CA42_VENDOR_ID 0x10b5
#define CA_42_CA42_PRODUCT_ID 0xac70
#define CA_42_CA42_VENDOR_ID 0x10b5
#define CA_42_CA42_PRODUCT_ID 0xac70
#define SAGEM_VENDOR_ID 0x079b
#define SAGEM_PRODUCT_ID 0x0027
#define SAGEM_VENDOR_ID 0x079b
#define SAGEM_PRODUCT_ID 0x0027
/* Leadtek GPS 9531 (ID 0413:2101) */
#define LEADTEK_VENDOR_ID 0x0413
#define LEADTEK_9531_PRODUCT_ID 0x2101
#define LEADTEK_VENDOR_ID 0x0413
#define LEADTEK_9531_PRODUCT_ID 0x2101
/* USB GSM cable from Speed Dragon Multimedia, Ltd */
#define SPEEDDRAGON_VENDOR_ID 0x0e55
#define SPEEDDRAGON_PRODUCT_ID 0x110b
#define SPEEDDRAGON_VENDOR_ID 0x0e55
#define SPEEDDRAGON_PRODUCT_ID 0x110b
/* DATAPILOT Universal-2 Phone Cable */
#define DATAPILOT_U2_VENDOR_ID 0x0731
#define DATAPILOT_U2_PRODUCT_ID 0x2003
#define DATAPILOT_U2_VENDOR_ID 0x0731
#define DATAPILOT_U2_PRODUCT_ID 0x2003
/* Belkin "F5U257" Serial Adapter */
#define BELKIN_VENDOR_ID 0x050d
#define BELKIN_PRODUCT_ID 0x0257
#define BELKIN_VENDOR_ID 0x050d
#define BELKIN_PRODUCT_ID 0x0257
/* Alcor Micro Corp. USB 2.0 TO RS-232 */
#define ALCOR_VENDOR_ID 0x058F
#define ALCOR_PRODUCT_ID 0x9720
#define ALCOR_VENDOR_ID 0x058F
#define ALCOR_PRODUCT_ID 0x9720
/* Willcom WS002IN Data Driver (by NetIndex Inc.) */
#define WS002IN_VENDOR_ID 0x11f6
#define WS002IN_PRODUCT_ID 0x2001
#define WS002IN_VENDOR_ID 0x11f6
#define WS002IN_PRODUCT_ID 0x2001
/* Corega CG-USBRS232R Serial Adapter */
#define COREGA_VENDOR_ID 0x07aa
#define COREGA_PRODUCT_ID 0x002a
#define COREGA_VENDOR_ID 0x07aa
#define COREGA_PRODUCT_ID 0x002a
/* Y.C. Cable U.S.A., Inc - USB to RS-232 */
#define YCCABLE_VENDOR_ID 0x05ad
#define YCCABLE_PRODUCT_ID 0x0fba
#define YCCABLE_VENDOR_ID 0x05ad
#define YCCABLE_PRODUCT_ID 0x0fba
/* "Superial" USB - Serial */
#define SUPERIAL_VENDOR_ID 0x5372
#define SUPERIAL_PRODUCT_ID 0x2303
#define SUPERIAL_VENDOR_ID 0x5372
#define SUPERIAL_PRODUCT_ID 0x2303
/* Hewlett-Packard LD220-HP POS Pole Display */
#define HP_VENDOR_ID 0x03f0
#define HP_LD220_PRODUCT_ID 0x3524
#define HP_VENDOR_ID 0x03f0
#define HP_LD220_PRODUCT_ID 0x3524
/* Cressi Edy (diving computer) PC interface */
#define CRESSI_VENDOR_ID 0x04b8
#define CRESSI_EDY_PRODUCT_ID 0x0521
#define CRESSI_VENDOR_ID 0x04b8
#define CRESSI_EDY_PRODUCT_ID 0x0521
/* Zeagle dive computer interface */
#define ZEAGLE_VENDOR_ID 0x04b8
#define ZEAGLE_N2ITION3_PRODUCT_ID 0x0522
#define ZEAGLE_VENDOR_ID 0x04b8
#define ZEAGLE_N2ITION3_PRODUCT_ID 0x0522
/* Sony, USB data cable for CMD-Jxx mobile phones */
#define SONY_VENDOR_ID 0x054c
#define SONY_QN3USB_PRODUCT_ID 0x0437
#define SONY_VENDOR_ID 0x054c
#define SONY_QN3USB_PRODUCT_ID 0x0437
/* Sanwa KB-USB2 multimeter cable (ID: 11ad:0001) */
#define SANWA_VENDOR_ID 0x11ad
#define SANWA_PRODUCT_ID 0x0001
#define SANWA_VENDOR_ID 0x11ad
#define SANWA_PRODUCT_ID 0x0001
/* ADLINK ND-6530 RS232,RS485 and RS422 adapter */
#define ADLINK_VENDOR_ID 0x0b63
#define ADLINK_ND6530_PRODUCT_ID 0x6530
#define ADLINK_VENDOR_ID 0x0b63
#define ADLINK_ND6530_PRODUCT_ID 0x6530
/* SMART USB Serial Adapter */
#define SMART_VENDOR_ID 0x0b8c
#define SMART_PRODUCT_ID 0x2303
#define SMART_VENDOR_ID 0x0b8c
#define SMART_PRODUCT_ID 0x2303

1
include/hw/s390x/s390-virtio-ccw.h
View File

@ -27,7 +27,6 @@ struct S390CcwMachineState {
bool aes_key_wrap;
bool dea_key_wrap;
bool pv;
bool zpcii_disable;
uint8_t loadparm[8];
};

100
include/hw/usb.h
View File

@ -66,42 +66,42 @@
//#define USB_STATE_POWERED 2
#define USB_STATE_DEFAULT 3
//#define USB_STATE_ADDRESS 4
//#define USB_STATE_CONFIGURED 5
//#define USB_STATE_CONFIGURED 5
#define USB_STATE_SUSPENDED 6
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_CSCID 0x0b
#define USB_CLASS_CONTENT_SEC 0x0d
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_CSCID 0x0b
#define USB_CLASS_CONTENT_SEC 0x0d
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
#define USB_SUBCLASS_UNDEFINED 0
#define USB_SUBCLASS_AUDIO_CONTROL 1
#define USB_SUBCLASS_AUDIO_STREAMING 2
#define USB_SUBCLASS_AUDIO_MIDISTREAMING 3
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
#define USB_TYPE_MASK (0x03 << 5)
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
#define USB_TYPE_MASK (0x03 << 5)
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
#define USB_RECIP_MASK 0x1f
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define USB_RECIP_MASK 0x1f
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define DeviceRequest ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define DeviceOutRequest ((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
@ -126,28 +126,28 @@
#define EndpointOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_ENDPOINT)<<8)
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_REQ_SET_SEL 0x30
#define USB_REQ_SET_ISOCH_DELAY 0x31
#define USB_DEVICE_SELF_POWERED 0
#define USB_DEVICE_REMOTE_WAKEUP 1
#define USB_DEVICE_SELF_POWERED 0
#define USB_DEVICE_REMOTE_WAKEUP 1
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE_QUALIFIER 0x06
#define USB_DT_OTHER_SPEED_CONFIG 0x07
#define USB_DT_DEBUG 0x0A
@ -167,10 +167,10 @@
#define USB_CFG_ATT_WAKEUP (1 << 5)
#define USB_CFG_ATT_BATTERY (1 << 4)
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_XFER_INVALID 255
#define USB_INTERFACE_INVALID 255
@ -569,9 +569,9 @@ static inline bool usb_device_is_scsi_storage(USBDevice *dev)
/* quirks.c */
/* In bulk endpoints are streaming data sources (iow behave like isoc eps) */
#define USB_QUIRK_BUFFER_BULK_IN 0x01
#define USB_QUIRK_BUFFER_BULK_IN 0x01
/* Bulk pkts in FTDI format, need special handling when combining packets */
#define USB_QUIRK_IS_FTDI 0x02
#define USB_QUIRK_IS_FTDI 0x02
int usb_get_quirks(uint16_t vendor_id, uint16_t product_id,
uint8_t interface_class, uint8_t interface_subclass,

1506
include/hw/usb/dwc2-regs.h
View File

File diff suppressed because it is too large Load Diff

8
qemu-options.hx
View File

@ -37,8 +37,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
" memory-encryption=@var{} memory encryption object to use (default=none)\n"
" hmat=on|off controls ACPI HMAT support (default=off)\n"
" memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n"
" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n"
" zpcii-disable=on|off disables zPCI interpretation facilities (default=off)\n",
" cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n",
QEMU_ARCH_ALL)
SRST
``-machine [type=]name[,prop=value[,...]]``
@ -158,11 +157,6 @@ SRST
::
-machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512k
``zpcii-disable=on|off``
Disables zPCI interpretation facilties on s390-ccw hosts.
This feature can be used to disable hardware virtual assists
related to zPCI devices. The default is off.
ERST
DEF("M", HAS_ARG, QEMU_OPTION_M,

9214
ui/vgafont.h
View File

File diff suppressed because it is too large Load Diff

20
ui/vnc-enc-zywrle-template.c
View File

@ -86,17 +86,17 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#undef L_2
#if ZYWRLE_ENDIAN == ENDIAN_BIG
# define S_0 1
# define S_1 0
# define L_0 3
# define L_1 2
# define L_2 1
# define S_0 1
# define S_1 0
# define L_0 3
# define L_1 2
# define L_2 1
#else
# define S_0 0
# define S_1 1
# define L_0 0
# define L_1 1
# define L_2 2
# define S_0 0
# define S_1 1
# define L_0 0
# define L_1 1
# define L_2 2
#endif
#define ZYWRLE_QUANTIZE

16
ui/vnc-enc-zywrle.h
View File

@ -51,14 +51,14 @@ static const unsigned int zywrle_param[3][3]={
{0x0000F000, 0x00000000, 0x00000000},
{0x0000C000, 0x00F0F0F0, 0x00000000},
{0x0000C000, 0x00C0C0C0, 0x00F0F0F0},
/* {0x0000FF00, 0x00000000, 0x00000000},
/* {0x0000FF00, 0x00000000, 0x00000000},
{0x0000FF00, 0x00FFFFFF, 0x00000000},
{0x0000FF00, 0x00FFFFFF, 0x00FFFFFF}, */
};
#else
/* Type B:Non liner quantization filter. */
static const int8_t zywrle_conv[4][256]={
{ /* bi=5, bo=5 r=0.0:PSNR=24.849 */
{ /* bi=5, bo=5 r=0.0:PSNR=24.849 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -92,7 +92,7 @@ static const int8_t zywrle_conv[4][256]={
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{ /* bi=5, bo=5 r=2.0:PSNR=74.031 */
{ /* bi=5, bo=5 r=2.0:PSNR=74.031 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 32,
@ -126,7 +126,7 @@ static const int8_t zywrle_conv[4][256]={
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{ /* bi=5, bo=4 r=2.0:PSNR=64.441 */
{ /* bi=5, bo=4 r=2.0:PSNR=64.441 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -160,7 +160,7 @@ static const int8_t zywrle_conv[4][256]={
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{ /* bi=5, bo=2 r=2.0:PSNR=43.175 */
{ /* bi=5, bo=2 r=2.0:PSNR=43.175 */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -274,14 +274,14 @@ static inline void harr(int8_t *px0, int8_t *px1)
x1 += x0;
if (((x1 ^ orgx1) & 0x80) == 0) {
/* |x1| > |x0| */
x0 -= x1; /* H = -B */
x0 -= x1; /* H = -B */
}
} else {
/* same sign */
x0 -= x1;
if (((x0 ^ orgx0) & 0x80) == 0) {
/* |x0| > |x1| */
x1 += x0; /* L = A */
x1 += x0; /* L = A */
}
}
*px0 = (int8_t)x1;
@ -585,7 +585,7 @@ static inline void wavelet(int *buf, int width, int height, int level)
} \
} while (0)
#define ZYWRLE_PACK_COEFF(buf, data, t, width, height, scanline, level) \
#define ZYWRLE_PACK_COEFF(buf, data, t, width, height, scanline, level) \
ZYWRLE_TRANSFER_COEFF(buf, data, t, width, height, scanline, level, \
ZYWRLE_LOAD_COEFF(ph, r, g, b); \
ZYWRLE_SAVE_PIXEL(data, r, g, b);)

2
ui/vnc_keysym.h
View File

@ -102,7 +102,7 @@ static const name2keysym_t name2keysym[]={
/* latin 1 extensions */
{ "nobreakspace", 0x0a0},
{ "exclamdown", 0x0a1},
{ "cent", 0x0a2},
{ "cent", 0x0a2},
{ "sterling", 0x0a3},
{ "currency", 0x0a4},
{ "yen", 0x0a5},

4
util/qemu-config.c
View File

@ -236,10 +236,6 @@ static QemuOptsList machine_opts = {
.help = "Up to 8 chars in set of [A-Za-z0-9. ](lower case chars"
" converted to upper case) to pass to machine"
" loader, boot manager, and guest kernel",
},{
.name = "zpcii-disable",
.type = QEMU_OPT_BOOL,
.help = "disable zPCI interpretation facilities",
},
{ /* End of list */ }
}