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target-mips: correct MFC0 for CP0.EntryLo in MIPS64 

CP0.EntryLo bits 31:30 have to be cleared.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Leon Alrae 2015-03-20 12:06:10 +00:00
parent bd8f1ebce4
commit b435f3f3d1
1 changed files with 6 additions and 6 deletions
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12
target-mips/translate.c
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@ -4964,10 +4964,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
/* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new();
tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
tcg_gen_shri_tl(tmp, tmp, 32);
tcg_gen_or_tl(arg, arg, tmp);
tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI);
tcg_gen_deposit_tl(arg, arg, tmp, 30, 2);
tcg_temp_free(tmp);
}
#endif
@ -5019,10 +5019,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
#if defined(TARGET_MIPS64)
if (ctx->rxi) {
/* Move RI/XI fields to bits 31:30 */
TCGv tmp = tcg_temp_new();
tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
tcg_gen_shri_tl(tmp, tmp, 32);
tcg_gen_or_tl(arg, arg, tmp);
tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI);
tcg_gen_deposit_tl(arg, arg, tmp, 30, 2);
tcg_temp_free(tmp);
}
#endif