x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled
Emulate the interrupt remapping support when guest virtual APIC is not enabled. For more info Refer: AMD IOMMU spec Rev 3.0 - section 2.2.5.1 When VAPIC is not enabled, it uses interrupt remapping as defined in Table 20 and Figure 15 from IOMMU spec. Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Cc: Peter Xu <peterx@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Cc: Tom Lendacky <Thomas.Lendacky@amd.com> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Singh, Brijesh
Michael S. Tsirkin
parent
577c470f43
commit
b44159fe00
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@ -28,6 +28,7 @@
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#include "qemu/error-report.h"
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#include "hw/i386/apic_internal.h"
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#include "trace.h"
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#include "hw/i386/apic-msidef.h"
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/* used AMD-Vi MMIO registers */
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const char *amdvi_mmio_low[] = {
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@ -1032,21 +1033,146 @@ static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
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return ret;
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}
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static int amdvi_get_irte(AMDVIState *s, MSIMessage *origin, uint64_t *dte,
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union irte *irte, uint16_t devid)
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{
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uint64_t irte_root, offset;
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irte_root = dte[2] & AMDVI_IR_PHYS_ADDR_MASK;
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offset = (origin->data & AMDVI_IRTE_OFFSET) << 2;
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trace_amdvi_ir_irte(irte_root, offset);
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if (dma_memory_read(&address_space_memory, irte_root + offset,
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irte, sizeof(*irte))) {
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trace_amdvi_ir_err("failed to get irte");
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return -AMDVI_IR_GET_IRTE;
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}
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trace_amdvi_ir_irte_val(irte->val);
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return 0;
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}
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static int amdvi_int_remap_legacy(AMDVIState *iommu,
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MSIMessage *origin,
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MSIMessage *translated,
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uint64_t *dte,
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X86IOMMUIrq *irq,
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uint16_t sid)
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{
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int ret;
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union irte irte;
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/* get interrupt remapping table */
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ret = amdvi_get_irte(iommu, origin, dte, &irte, sid);
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if (ret < 0) {
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return ret;
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}
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if (!irte.fields.valid) {
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trace_amdvi_ir_target_abort("RemapEn is disabled");
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return -AMDVI_IR_TARGET_ABORT;
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}
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if (irte.fields.guest_mode) {
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error_report_once("guest mode is not zero");
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return -AMDVI_IR_ERR;
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}
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if (irte.fields.int_type > AMDVI_IOAPIC_INT_TYPE_ARBITRATED) {
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error_report_once("reserved int_type");
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return -AMDVI_IR_ERR;
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}
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irq->delivery_mode = irte.fields.int_type;
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irq->vector = irte.fields.vector;
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irq->dest_mode = irte.fields.dm;
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irq->redir_hint = irte.fields.rq_eoi;
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irq->dest = irte.fields.destination;
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return 0;
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}
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static int __amdvi_int_remap_msi(AMDVIState *iommu,
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MSIMessage *origin,
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MSIMessage *translated,
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uint64_t *dte,
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X86IOMMUIrq *irq,
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uint16_t sid)
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{
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uint8_t int_ctl;
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int_ctl = (dte[2] >> AMDVI_IR_INTCTL_SHIFT) & 3;
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trace_amdvi_ir_intctl(int_ctl);
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switch (int_ctl) {
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case AMDVI_IR_INTCTL_PASS:
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memcpy(translated, origin, sizeof(*origin));
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return 0;
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case AMDVI_IR_INTCTL_REMAP:
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break;
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case AMDVI_IR_INTCTL_ABORT:
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trace_amdvi_ir_target_abort("int_ctl abort");
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return -AMDVI_IR_TARGET_ABORT;
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default:
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trace_amdvi_ir_err("int_ctl reserved");
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return -AMDVI_IR_ERR;
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}
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return amdvi_int_remap_legacy(iommu, origin, translated, dte, irq, sid);
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}
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/* Interrupt remapping for MSI/MSI-X entry */
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static int amdvi_int_remap_msi(AMDVIState *iommu,
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MSIMessage *origin,
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MSIMessage *translated,
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uint16_t sid)
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{
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int ret = 0;
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uint64_t pass = 0;
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uint64_t dte[4] = { 0 };
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X86IOMMUIrq irq = { 0 };
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uint8_t dest_mode, delivery_mode;
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assert(origin && translated);
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/*
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* When IOMMU is enabled, interrupt remap request will come either from
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* IO-APIC or PCI device. If interrupt is from PCI device then it will
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* have a valid requester id but if the interrupt is from IO-APIC
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* then requester id will be invalid.
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*/
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if (sid == X86_IOMMU_SID_INVALID) {
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sid = AMDVI_IOAPIC_SB_DEVID;
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}
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trace_amdvi_ir_remap_msi_req(origin->address, origin->data, sid);
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if (!iommu || !X86_IOMMU_DEVICE(iommu)->intr_supported) {
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/* check if device table entry is set before we go further. */
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if (!iommu || !iommu->devtab_len) {
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memcpy(translated, origin, sizeof(*origin));
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goto out;
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}
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if (!amdvi_get_dte(iommu, sid, dte)) {
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return -AMDVI_IR_ERR;
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}
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/* Check if IR is enabled in DTE */
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if (!(dte[2] & AMDVI_IR_REMAP_ENABLE)) {
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memcpy(translated, origin, sizeof(*origin));
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goto out;
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}
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/* validate that we are configure with intremap=on */
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if (!X86_IOMMU_DEVICE(iommu)->intr_supported) {
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trace_amdvi_err("Interrupt remapping is enabled in the guest but "
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"not in the host. Use intremap=on to enable interrupt "
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"remapping in amd-iommu.");
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return -AMDVI_IR_ERR;
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}
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if (origin->address & AMDVI_MSI_ADDR_HI_MASK) {
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trace_amdvi_err("MSI address high 32 bits non-zero when "
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"Interrupt Remapping enabled.");
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@ -1058,10 +1184,81 @@ static int amdvi_int_remap_msi(AMDVIState *iommu,
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return -AMDVI_IR_ERR;
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}
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/*
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* The MSI data register [10:8] are used to get the upstream interrupt type.
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*
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* See MSI/MSI-X format:
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* https://pdfs.semanticscholar.org/presentation/9420/c279e942eca568157711ef5c92b800c40a79.pdf
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* (page 5)
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*/
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delivery_mode = (origin->data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 7;
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switch (delivery_mode) {
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case AMDVI_IOAPIC_INT_TYPE_FIXED:
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case AMDVI_IOAPIC_INT_TYPE_ARBITRATED:
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trace_amdvi_ir_delivery_mode("fixed/arbitrated");
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ret = __amdvi_int_remap_msi(iommu, origin, translated, dte, &irq, sid);
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if (ret < 0) {
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goto remap_fail;
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} else {
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/* Translate IRQ to MSI messages */
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x86_iommu_irq_to_msi_message(&irq, translated);
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goto out;
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}
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break;
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case AMDVI_IOAPIC_INT_TYPE_SMI:
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error_report("SMI is not supported!");
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ret = -AMDVI_IR_ERR;
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break;
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case AMDVI_IOAPIC_INT_TYPE_NMI:
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pass = dte[3] & AMDVI_DEV_NMI_PASS_MASK;
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trace_amdvi_ir_delivery_mode("nmi");
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break;
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case AMDVI_IOAPIC_INT_TYPE_INIT:
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pass = dte[3] & AMDVI_DEV_INT_PASS_MASK;
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trace_amdvi_ir_delivery_mode("init");
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break;
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case AMDVI_IOAPIC_INT_TYPE_EINT:
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pass = dte[3] & AMDVI_DEV_EINT_PASS_MASK;
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trace_amdvi_ir_delivery_mode("eint");
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break;
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default:
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trace_amdvi_ir_delivery_mode("unsupported delivery_mode");
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ret = -AMDVI_IR_ERR;
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break;
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}
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if (ret < 0) {
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goto remap_fail;
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}
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/*
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* The MSI address register bit[2] is used to get the destination
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* mode. The dest_mode 1 is valid for fixed and arbitrated interrupts
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* only.
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*/
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dest_mode = (origin->address >> MSI_ADDR_DEST_MODE_SHIFT) & 1;
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if (dest_mode) {
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trace_amdvi_ir_err("invalid dest_mode");
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ret = -AMDVI_IR_ERR;
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goto remap_fail;
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}
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if (pass) {
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memcpy(translated, origin, sizeof(*origin));
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} else {
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trace_amdvi_ir_err("passthrough is not enabled");
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ret = -AMDVI_IR_ERR;
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goto remap_fail;
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}
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out:
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trace_amdvi_ir_remap_msi(origin->address, origin->data,
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translated->address, translated->data);
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return 0;
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remap_fail:
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return ret;
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}
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static int amdvi_int_remap(X86IOMMUState *iommu,
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@ -217,7 +217,51 @@
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/* Interrupt remapping errors */
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#define AMDVI_IR_ERR 0x1
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#define AMDVI_IR_GET_IRTE 0x2
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#define AMDVI_IR_TARGET_ABORT 0x3
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/* Interrupt remapping */
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#define AMDVI_IR_REMAP_ENABLE 1ULL
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#define AMDVI_IR_INTCTL_SHIFT 60
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#define AMDVI_IR_INTCTL_ABORT 0
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#define AMDVI_IR_INTCTL_PASS 1
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#define AMDVI_IR_INTCTL_REMAP 2
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#define AMDVI_IR_PHYS_ADDR_MASK (((1ULL << 45) - 1) << 6)
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/* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */
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#define AMDVI_IRTE_OFFSET 0x7ff
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/* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */
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#define AMDVI_IOAPIC_INT_TYPE_FIXED 0x0
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#define AMDVI_IOAPIC_INT_TYPE_ARBITRATED 0x1
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#define AMDVI_IOAPIC_INT_TYPE_SMI 0x2
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#define AMDVI_IOAPIC_INT_TYPE_NMI 0x4
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#define AMDVI_IOAPIC_INT_TYPE_INIT 0x5
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#define AMDVI_IOAPIC_INT_TYPE_EINT 0x7
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/* Pass through interrupt */
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#define AMDVI_DEV_INT_PASS_MASK (1UL << 56)
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#define AMDVI_DEV_EINT_PASS_MASK (1UL << 57)
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#define AMDVI_DEV_NMI_PASS_MASK (1UL << 58)
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#define AMDVI_DEV_LINT0_PASS_MASK (1UL << 62)
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#define AMDVI_DEV_LINT1_PASS_MASK (1UL << 63)
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/* Interrupt remapping table fields (Guest VAPIC not enabled) */
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union irte {
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uint32_t val;
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struct {
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uint32_t valid:1,
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no_fault:1,
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int_type:3,
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rq_eoi:1,
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dm:1,
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guest_mode:1,
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destination:8,
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vector:8,
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rsvd:8;
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} fields;
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};
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#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
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#define AMD_IOMMU_DEVICE(obj)\
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@ -106,6 +106,13 @@ amdvi_mem_ir_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" data 0x%"PRIx6
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amdvi_ir_remap_msi_req(uint64_t addr, uint64_t data, uint8_t devid) "addr 0x%"PRIx64" data 0x%"PRIx64" devid 0x%"PRIx8
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amdvi_ir_remap_msi(uint64_t addr, uint64_t data, uint64_t addr2, uint64_t data2) "(addr 0x%"PRIx64", data 0x%"PRIx64") -> (addr 0x%"PRIx64", data 0x%"PRIx64")"
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amdvi_err(const char *str) "%s"
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amdvi_ir_irte(uint64_t addr, uint64_t data) "addr 0x%"PRIx64" offset 0x%"PRIx64
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amdvi_ir_irte_val(uint32_t data) "data 0x%"PRIx32
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amdvi_ir_err(const char *str) "%s"
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amdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8
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amdvi_ir_target_abort(const char *str) "%s"
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amdvi_ir_delivery_mode(const char *str) "%s"
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amdvi_ir_generate_msi_message(uint8_t vector, uint8_t delivery_mode, uint8_t dest_mode, uint8_t dest, uint8_t rh) "vector %d delivery-mode %d dest-mode %d dest-id %d rh %d"
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# hw/i386/vmport.c
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vmport_register(unsigned char command, void *func, void *opaque) "command: 0x%02x func: %p opaque: %p"
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